Preprocessing Steiner problems from VLSI layout

Abstract

VLSI layout applications yield instances of the Steiner tree problem over grid graphs with holes, which are considered hard to be solved by current methods. In particular, preprocessing techniques developed for Steiner problems over general graphs are not likely to reduce, significantly, such VLSI instances. We propose a new preprocessing procedure, extending earlier ideas from the literature and improving their application, so as to make them effective for VLSI problems. We report significant reductions within reasonable computational times, obtained with the application of this procedure to 116 instances of the SteinLib. These reductions allowed a branch and cut to solve 28 of 32 open instances of the SteinLib, some with more than 10,000 vertices and 20,000 edges.

Reduction tests for the prize-collecting Steiner problem

“…The sequence of results reported in [13,15,16,19,17,14,12] on the main benchmark instances from the literature [8] improve by two or three orders of magnitude upon the results from previous articles, like [7]. The strength of those new algorithms lies on a complex combination of reduction tests, primal heuristics, dual heuristics and branch-and-cut.…”

“…The most important such tests are based on the concept of bottleneck Steiner distances. More recently, Uchoa et al [17] enhanced Duin and Volgenant's tests with the idea of expansion. This idea was further developed by Polzin and Vahdati [14].…”

“…The new tests introduced in Uchoa et al [17] are enhancements of the SD and the NTD-k tests with the idea of expansion. Loosely speaking, this idea means probing the instance to dynamically build a chain of logical implications of the kind "if edge e appear in some optimal solution R then edge f must also be in R" in order to prove that some graph reduction can be indeed performed.…”

The Steiner Tree Problem with Delays: A compact formulation and reduction procedures

“…, [21], [27], [4], [28]). Quite simple reduction tests for the STP are the degree tests applied recursively to each reduced graph, until no more reduction can be performed.…”

Finding Steiner trees with degree 1 terminal nodes

“…The Steiner Problem in Graphs and its variants is an useful model for a number of circuit design and communication network design problems [2,7,9]. We study here an important variant of the problem: suppose we have a fixed node z (called the root), and that we want to connect all nodes in T to z (eventually using some Steiner nodes), in such a way that all nodes in T have degree 1 in the optimal solution (i.e., terminal sites can not be used as intermediate nodes; this implies in particular that connections between pairs of terminal sites are not allowed).…”