Preplacement Net Length and Timing Estimation by Customized Graph Neural Network

Xie, Zhiyao; Liang, Rongjian; Xu, Xiaoqing; Hu, Jiang; Chang, Chen-Chia; Pan, Jingyu; Chen, Yiran

doi:10.1109/tcad.2022.3149977

Cited by 11 publications

(2 citation statements)

References 27 publications

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“…However, accurate timing information can be accessed only after routing stage, which is time-consuming. To estimate pre-routing timing metrics, machine learning has been introduced for timing prediction, such as delay (Barboza et al 2019;Yang, He, and Cao 2022), wirelength (Xie et al 2021;, to guide timing-driven cell placement.…”

Section: Introductionmentioning

confidence: 99%

“…However, in circuits graphs, signals travel from primary inputs to timing endpoints, forming long timing paths (Hu, Sinha, and Keller 2014), where long range dependencies and global view play a critical role but they are hard for typical GNN to handle. Previous methods for other timing metric (delay, wirelength) prediction (Xie et al 2018;Barboza et al 2019;Ghose et al 2021;Xie et al 2021;Yang, He, and Cao 2022; (Guo et al 2022) utilizes a timing engine inspired GNN to predict slack, where node embedding is updated with predecessors asynchronously. However, it is prone to signal decay and error accumulation, demonstrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

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PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling

Zhong,

Ye,

Tang

et al. 2024

AAAI

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Pre-routing timing prediction has been recently studied for evaluating the quality of a candidate cell placement in chip design. It involves directly estimating the timing metrics for both pin-level (slack, slew) and edge-level (net delay, cell delay), without time-consuming routing. However, it often suffers from signal decay and error accumulation due to the long timing paths in large-scale industrial circuits. To address these challenges, we propose a two-stage approach. First, we propose global circuit training to pre-train a graph auto-encoder that learns the global graph embedding from circuit netlist. Second, we use a novel node updating scheme for message passing on GCN, following the topological sorting sequence of the learned graph embedding and circuit graph. This scheme residually models the local time delay between two adjacent pins in the updating sequence, and extracts the lookup table information inside each cell via a new attention mechanism. To handle large-scale circuits efficiently, we introduce an order preserving partition scheme that reduces memory consumption while maintaining the topological dependencies. Experiments on 21 real world circuits achieve a new SOTA R2 of 0.93 for slack prediction, which is significantly surpasses 0.59 by previous SOTA method. Code will be available at: https://github.com/Thinklab-SJTU/EDA-AI.

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Section: Introductionmentioning

confidence: 99%