Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects

Pathade, Takshashila; Shah, Urmi; Agrawal, Yash; Parekh, Rutu

doi:10.1109/edaps.2018.8680882

Cited by 5 publications

(1 citation statement)

References 7 publications

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“…Crosstalk has become the most critical concern in modern sub-10 nm integrated circuits [ 14 ]. This coupling causes problems that can be addressed by various methods like shielding [ 15 , 16 , 17 , 18 , 19 , 20 ], inserting repeaters [ 21 , 22 , 23 , 24 , 25 ] or buffers [ 26 , 27 , 28 , 29 , 30 , 31 ], duplication [ 32 ] and crosstalk avoidance code (CAC) [ 33 , 34 , 35 , 36 ]. Insertion of buffers and shielding has more area cost when compared to duplication or CAC [ 37 ].…”

Section: Introductionmentioning

confidence: 99%

A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend

et al. 2023

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Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

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