Predictive scheduling of network processors

Wolf, Tilman; Pappu, Prashanth; Franklin, Mark A.

doi:10.1016/s1389-1286(02)00452-8

Cited by 26 publications

(11 citation statements)

References 24 publications

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“…Therefore, each arriving packet can be allocated to any arbitrary PE for processing. As commonly assumed, we consider a single stream of incoming packets [16], [22]- [25]. We allow arbitrary arrival times of the packets, and assume infinite buffer sizes.…”

Section: System Model and Problem Formulation A System Modelmentioning

confidence: 99%

Scaling multi-core network processors without the reordering bottleneck

Shpiner

Keslassy

Cohen³

2014

2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR)

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Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks.

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Section: System Model and Problem Formulation A System Modelmentioning

confidence: 99%

Scaling multi-core network processors without the reordering bottleneck

Shpiner

Keslassy

Cohen³

2014

2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR)

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“…ADAG should allow to identify parallelizable application parts. Several methodologies have been proposed in order to map workloads on multicore network processors according to ADAG's profiling results [32] or other profiling analysis [8,33,14,20,26]. However, current proposals are focused on Layer 2-3 applications in order to maximize resource utilization.…”

Section: Related Workmentioning

confidence: 99%

MultiLayer processing - an execution model for parallel stateful packet processing

Verdú

Nemirovsky

Valero

2008

Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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Mostly emerging network applications comprise deep packet inspection and/or stateful capabilities. Stateful workloads present limitations that reduce the exploitation of parallelism, unlike other network applications that show marginal dependencies among packets. In addition, differences among packet processing lead to significant negative interaction between threads, especially in the memory hierarchy.We propose MultiLayer Processing (MLP) as an execution model to properly exploit the levels of parallelism of stateful applications. The goal of MLP is to increase the system throughput by increasing the synergy among threads in the memory hierarchy, and alleviating the contention in critical sections of parallel workloads. We show that MLP presents about 2.4x higher throughput than other execution models with large processor architectures.

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“…Ramaswamy et al [5] use "criticality" as task priority. Wolf et al [6] propose two predictive scheduling algorithms, LAP and EFQ, both of which are in nature based on list scheduling. The basic idea of randomized mapping is to randomly choose a valid mapping and evaluate its performance and repeat this process certain times.…”

Section: Related Workmentioning

confidence: 99%

Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors

Yang

Zhang

et al.

Lecture Notes in Computer Science

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Abstract. It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on-Chip. This paper proposes a novel scheduling algorithm, called Replication-based Partial Dynamic Scheduling (RPDS). It aims to improve the NP performance by combining the strategies of partial dynamic mapping and task replication with a 2-phase scheduling. RPDS differs from existing solutions in several aspects, e.g., the processing elements are heterogeneous, fully-connected, and multi-threading, the application is decomposed into directed acyclic graph tasks with continuous data-packets, and scheduling is conducted at both of initialization and run-time. Experimental results showed our algorithm could increase the largest average throughput by about 30% than those without dynamic phase replication.

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Predictive scheduling of network processors

Cited by 26 publications

References 24 publications

Scaling multi-core network processors without the reordering bottleneck

Scaling multi-core network processors without the reordering bottleneck

MultiLayer processing - an execution model for parallel stateful packet processing

Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors

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