2012
DOI: 10.1016/j.microrel.2012.04.004
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Prediction of damage and fatigue life of high-temperature flip chip assembly interconnections at operations

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Cited by 15 publications
(3 citation statements)
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“…Formation of complete hysteresis loop up to the sixth thermal cycles supports earlier finding reported by Amalu and Ekere [28] and thus the authors emphasise the use of at least six temperature cycles in thermo-mechanical investigation of solder joints in not only electronic assemblies but also in photovoltaic modules. The results of the computation of fatigue life of the solder joints using the two relations demonstrates that the employment of creep strain energy and the model based on it give a better result than creep strain and its model.…”
Section: Discussionsupporting
confidence: 86%
“…Formation of complete hysteresis loop up to the sixth thermal cycles supports earlier finding reported by Amalu and Ekere [28] and thus the authors emphasise the use of at least six temperature cycles in thermo-mechanical investigation of solder joints in not only electronic assemblies but also in photovoltaic modules. The results of the computation of fatigue life of the solder joints using the two relations demonstrates that the employment of creep strain energy and the model based on it give a better result than creep strain and its model.…”
Section: Discussionsupporting
confidence: 86%
“…Several researches have investigated the effect of intermetallic compound (IMC) layer on solder joint reliability (Amalu et al, 2011;Ekere, 2012a, 2012b;George, 2010;Nadimpalli and Spelt, 2011;Xiao et al, 2013). Amalu and Ekere, (2012a), in their prediction of damage and fatigue life of high-temperature flip chip assembly interconnections at operations, utillised 3D flip chip models simulated in ANSYS 13 to investgate the damage of bonded materials. They ascertained the IMC layer between solder and copper die as most vulnerable to crack initiation and propagation.…”
Section: Effect Of Cycle Number On Determination Of Accurate Degradatmentioning
confidence: 99%
“…Therefore, in the finite element modelling, the thickness of the silicon die is reduced to 33 µm, and the processing time of the solution in our PC (Intel i7 cpu and 16 gb memory) is about 100 hours. The solder joints are particularly vulnerable to crack initiations at the die-solder interconnect [8], resulting in great interest of the reliability of this region. The silicon die thickness of 33 µm was determined by calibrating the focal point of the virtual transducer into the middle of the UBM structure to achieve an optimal focus at the UBM structure.…”
Section: Finite Element Modellingmentioning
confidence: 99%