Prediction-based superpage-friendly TLB designs

Abstract

International audience—This work demonstrates that a set of commercial and scale-out applications exhibit significant use of superpages and thus suffer from the fixed and small superpage TLB structures of some modern core designs. Other processors better cope with superpages at the expense of using power-hungry and slow fully-associative TLBs. We consider alternate designs that allow all pages to freely share a single, power-efficient and fast set-associative TLB. We propose a prediction-guided multi-grain TLB design that uses a superpage prediction mechanism to avoid multiple lookups in the common case. In addition, we evaluate the previously proposed skewed TLB [1] which builds on principles similar to those used in skewed associative caches [2]. We enhance the original skewed TLB design by using page size prediction to increase its effective associativity. Our prediction-based multi-grain TLB design delivers more hits and is more power efficient than existing alternatives. The predictor uses a 32-byte prediction table indexed by base register values. I. INTRODUCTION Over the last 50 years virtual memory has been an intrinsic facility of computer systems, providing each process the illusion of an equally large and contiguous address space while enforcing isolation and access control. Page tables act as gate-keepers; they maintain the mappings of virtual pages to physical frames (i.e., translations) along with additional information (e.g., access privileges). Except for a reserved part of memory, any code or data structure which currently resides in the computer's physical memory has such a translation. Page tables are usually organized as multi-level, hierarchical tables with four levels being common for 64-bit systems. Therefore multiple sequential memory references are necessary to retrieve the translation of the smallest supported page size. Hardware Translation Lookaside Buffers (TLBs) cache translations which are the result of accessing the page table (page-walk). A TLB access is in the critical path of each instruction fetch and memory reference; the translation is needed to complete the tag comparison in physically-tagged L1 caches. Thus, a short TLB latency is crucial. There are technology trends that compound making TLB performance and energy critical in today's systems. Physical memory sizes and application footprints have been increasing without a commensurate increase in TLB size and thus coverage. As a result, while TLBs still reap the benefits of spatial and temporal locality due to their entries' coarse tracking granularity, they now fall short of growing workload footprints. The use of superpages (i.e., large contiguous virtual memory regions which map to contiguous physical frames) can exten

Energy-efficient address translation

“…Huge Pages [1,5] increase the TLB reach and reduce the performance overhead of page walks [13,15,36,41] by mapping a large fixed size region of memory with a single TLB entry [27,40,45,48]. For example, the x86-64 architecture allows a process to use 4 KB pages with 2 MB pages and 1 GB pages at the same time.…”

“…However, these energy optimization techniques do not take into account hardware support for increasing the TLB reach (e.g., huge pages), that primarily targets improving performance and reducing static energy overheads due to TLB misses. Only the recent work on TLB Pred [41] considers huge pages for improving the dynamic energy efficiency in TLBs. The performance of TLB Pred depends on huge pages successfully reducing misses, but prior work shows that huge pages can still incur high performance overheads due to TLB misses [13,15,36].…”

Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

“…Alternately, based on the observation that the majority of pages accessed per core on systems with superpage support are the smallest pages [38], we could avoid classifying superpages and consider them as coherent without significantly damaging system performance, while completely avoiding large pages overhead. Current systems supporting multiple page sizes implement multiple TLB structures to do so, thus the TLB actually storing large pages could classify them as shared without extra hardware support.…”

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

“…), which map to contiguous physical frames. Superpages improve TLB coverage, and can be stored in the same multi-grain TLB, or in a separate, single, full-associative TLB [58].…”

“…Alternately, based on the observation that the majority of pages accessed per core on systems with superpage support are the smallest pages [59], we could avoid classifying superpages and consider them as coherent without significantly damaging system performance, while completely avoiding large pages overhead. Current systems supporting multiple page sizes implement multiple TLB structures to do so, thus the TLB actually storing large pages could classify them as shared without extra hardware support.…”