Prediction-based power estimation and scheduling for CMPs

Singh, Karan; Bhadauria, Major; McKee, Sally A.

doi:10.1145/1542275.1542350

Cited by 6 publications

(6 citation statements)

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“…al. [26] derive an analytic, workloadindependent piece-wise linear power model that maps performance counters and temperature to power consumption. Laurenzano et.…”

Section: Related Workmentioning

confidence: 99%

“…al. [26]. Our work uses power measurements rather than models and we simultaneously treat clock frequency as a tunable parameter alongside the generation and evaluation of different code variants.…”

Section: Related Workmentioning

confidence: 99%

“…Modeling energy usage through combinations of architectural parameters with performance counters [26] or other resource usage information [21] also fall in this category. The second thrust, which invariably depends on the first, is to attempt to minimize the amount of energy required to solve various scientific problems.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Auto-tuning for Energy Usage in Scientific Applications

Tiwari

Laurenzano

Carrington

et al. 2012

Euro-Par 2011: Parallel Processing Workshops

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Abstract. The power wall has become a dominant impeding factor in the realm of exascale system design. It is therefore important to understand how to most effectively create application software in order to minimize its power usage while maintaining satisfactory levels of performance. In this work, we use existing software and hardware facilities in order to tune applications to minimize for several combinations of power and performance. The tuning is done with respect to software level performance-related tunables (cache tiling factors and loop unrolling factors) as well as for processor clock frequency. These tunable parameters are explored via an offline search in order to find the parameter combinations that are optimal with respect to performance (or delay, D), energy (E), energy×delay (E × D) and energy×delay×delay (E × D 2 ). These searches are employed on a parallel application that solves Poisson's equation using stencil computations. Stencil (nearestneighbor) computations are very common operations in today's scientific applications. We show that the parameter configuration that minimizes energy consumption can save, on average, 5.4% energy with a performance loss of 4% when compared to the configuration that minimizes runtime. Furthermore, with the work presented in this paper, we provide evidence for the existence of opportunities to auto-tune for energy in parallel applications.

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“…al. [26] derive an analytic, workloadindependent piece-wise linear power model that maps performance counters and temperature to power consumption. Laurenzano et.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Auto-tuning for Energy Usage in Scientific Applications

Tiwari

Laurenzano

Carrington

et al. 2012

Euro-Par 2011: Parallel Processing Workshops

View full text Add to dashboard Cite

show abstract

“…Various researchers have utilized hardware counters to develop power draw characterizations for HPC applications and kernels [21] [6] [16] [18]. Others have used processor performance events [4] and architectural parameters and parameters drawn from application's characteristics [14].…”

Section: Related Workmentioning

confidence: 99%

“…al. [21] derive an analytic, workload-independent piece-wise linear power model that maps performance counters and temperature to energy usage. Lively et.…”

Section: Related Workmentioning

confidence: 99%

Modeling Power and Energy Usage of HPC Kernels

Tiwari

Laurenzano

Carrington

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Abstract-Compute intensive kernels make up the majority of execution time in HPC applications. Therefore, many of the power draw and energy consumption traits of HPC applications can be characterized in terms of the power draw and energy consumption of these constituent kernels. Given that power and energy-related constraints have emerged as major design impediments for exascale systems, it is crucial to develop a greater understanding of how kernels behave in terms of power/energy when subjected to different compiler-based optimizations and different hardware settings. In this work, we develop CPU and DIMM power and energy models for three extensively utilized HPC kernels by training artificial neural networks. These networks are trained using empirical data gathered on the target architecture. The models utilize kernelspecific compiler-based optimization parameters and hardware tunables as inputs and make predictions for the power draw rate and energy consumption of system components. The resulting power draw and energy usage predictions have an absolute error rate that averages less than 5.5% for three important kernels -matrix multiplication (MM), stencil computation and LU factorization.

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Helper Thread Prefetching Control Framework on Chip Multi-processor

Zhang

Huang

et al. 2013

Int J Parallel Prog

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Prediction-based power estimation and scheduling for CMPs

Cited by 6 publications

References 0 publications

Auto-tuning for Energy Usage in Scientific Applications

Auto-tuning for Energy Usage in Scientific Applications

Modeling Power and Energy Usage of HPC Kernels

Helper Thread Prefetching Control Framework on Chip Multi-processor

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