12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06) 2006
DOI: 10.1109/rtcsa.2006.51
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Predictable Interrupt Scheduling with Low Overhead for Real-Time Kernels

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Cited by 14 publications
(12 citation statements)
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References 13 publications
(25 reference statements)
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“…The other four columns of the figure show the different executable entities in the system for four different interrupt management schemes. The rightmost column represents our integrated model [Leyva-del-Foyo et al 2006b, 2006c. The other three middle columns represent different classes of interrupt model.…”
Section: Related Workmentioning
confidence: 99%
“…The other four columns of the figure show the different executable entities in the system for four different interrupt management schemes. The rightmost column represents our integrated model [Leyva-del-Foyo et al 2006b, 2006c. The other three middle columns represent different classes of interrupt model.…”
Section: Related Workmentioning
confidence: 99%
“…To tackle this problem, Leyva-del-Foyo et al suggested to implement all tasks as threads, and to trigger them from very short interrupt handlers by posting a semaphore, for instance [5,6]. Furthermore, an interrupt-leveling mechanism implemented in software prevents any disturbance by lower-priority interrupt handlers by masking all corresponding interrupt sources.…”
Section: Rate-monotonic Priority Inversionmentioning
confidence: 99%
“…However, softwarebased approaches like the one presented in [5,6] suffer from the same problem. In those approaches, a small ISR is needed to notify the task related to the particular event-this ISR could completely utilize the CPU.…”
Section: Interrupt Overloadmentioning
confidence: 99%
“…Katcher et al emphasize the importance of integrating timer interrupts into the scheduling scheme in order to avoid unnecessary interrupts, i.e., timer interrupt that will wake up a low priority task while a higher priority task is in execution. This integrated interrupt model has been further extended by Leyva-del-Foyo et al in [6][7][8] to include all hardware interrupts that can be produced in a real-time kernel. These authors introduce an integrated model for task and interrupt management and propose different hardware and software implementation approaches.…”
Section: Introductionmentioning
confidence: 99%
“…The integration of hardware interrupts and real-time tasks gives rise to a real-time task set composed by Hardware Activated Tasks and Software Activated Tasks respectively [8]. The release of Harware Activated Task is strictly controlled by an Interrupt Hardware Abstraction Layer in [7] or more loosely controlled using an optimistic approach in [8].…”
Section: Introductionmentioning
confidence: 99%