Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

“…Various attempts have been made to improve the accuracy in device parameters [15][16][17][18]11] and in circuit performance parameters [16,19], and thereby increase the design accuracy.…”

“…Singh et al [17] have proposed to refine transistor models iteratively through regression over gradually shrinking design space. They have modeled g m and g d as a monomial function of W, L, I DS (without considering V DS or V SB dependency).…”

“…As a summary we can conclude that in [17,19,21] a number of SPICE simulations are required at the end of each GP iteration to improve the accuracy of either the device parameters or the circuit performance parameters or for the both. Therefore, efficiency of the equation-based sizing approach is directly sacrificed.…”

“…7, which is commonly used as a test example in most of the CAD literature [10,[15][16][17][18], has been considered as the first example circuit for comparison. Subsequently, relatively complex circuits such as single ended folded cascode opamp and fully differential folded cascode opamp also have been considered.…”

Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp

“…So this is called analog design bottleneck. In order to enhance design productivity, various computer-aided design (CAD) approaches have been presented for op amp design or analog circuit design [7][8][9][10][11][12][13][14].…”