Precision and performance of numerically controlled oscillators with hybrid function generators

Janiszewski, I.; Hoppe, B.; Meuth, H.

doi:10.1109/freq.2001.956374

Cited by 3 publications

(6 citation statements)

References 11 publications

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“…While the CORDIC algorithm may result in arbitrary precision, although at the expense of pipeline latency and internal bit resolution overhead, the alternative of using standard Look-Up Table (LUT) solutions leads to a silicon area rapidly increasing with bit-resolution, although with only moderate or no latency, as was discussed in detail for the rotation mode in [4], [5], [6]. For the vectoring mode, requiring a two-dimensional input for x and y, the resulting more complex LUT approach quickly grows out of proportion.…”

Section: Hybrid-vectoring Schemementioning

confidence: 97%

“…In earlier work, [4], [5], [6], a new hybrid scheme for the rotation mode was developed, effectively combining both advantages of CORDIC and LUT sshemes, whereby the preceding LUT eliminates a certain number of CORDIC iterations. Optimum partitioning between LUT and CORDIC, depending on resolution and other configuration parameters, produced designs of favorable silicon area and power consumption, available in a fully portable and parametrically configurable HDL format.…”

Section: Hybrid-vectoring Schemementioning

confidence: 99%

“…Here, Km,, is a scaling factor resulting from iterations starting at index m and ending with index n, and is defined as (4) i=m Note, that this scaling factor does not depend on the actual value sequence of qai, i.e. ICm,, is the same factor for all iteration paths with given starting index m and ending index n. After (n-m+l) iterations, the x-path value does thus not approach the desired magnitude value A but rather the dilated value A,, stretched by the factor (4).…”

Section: Introductionmentioning

confidence: 99%

“…If a particular application requires the actual magnitude value (l), the value resulting from the x-path has to be rescaled correspondingly by one single multiplication at the end. This specific COR-DIC problem can be circumvented only for the rotation mode by initializing the iteration sequence with suitably rescaled starting values for x and y, [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

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Pipeline-efficient hybrid vectoring implementation

Janiszewski

Meuth

Hoppe

Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234)

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Silicon area, power consumption and pipeline-emciency are investigated for hardware implementations of a Cartesian-to-polar (Le. both magnitude and phase) coordinate transformer (C2P). A novel hybrid scheme, consisting of both look-up and algorithmic constituents, is proposed, based on the VECTORING mode of the Coordinate Rotation Dlgital Computer (CORDIC) hardware algorithm, preceded by a principal axes transformation algorithm-derived look-up scheme. The iterative CORDIC algorithm is rigorous for infinite bit resolution, permitting in principle arbitrary precision, while its intrinsic sequential nature entails a substantial pipeline latency, and a high resolution overhead to combat finite iteration quantization error accumulation. Look-Up Table (LUT) size, due to the two Cartesian input dimensionality, increases rapidly with resolution and is thus limited to a small-resolution input data regime. Signal latencies may become essential e.g. for C2P inside a feedback loop. With the present hybrid scheme, numbers of iterations may be reduced by up to 50%, at no penalty or even at a reduction of silicon area and power consumption. Finally, such a hybrid architecture permits technology independent HDL models, a prerequisite for full portability and reuse.

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Section: Hybrid-vectoring Schemementioning

confidence: 97%

Section: Hybrid-vectoring Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Pipeline-efficient hybrid vectoring implementation

Janiszewski

Meuth

Hoppe

Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234)

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show abstract

“…Considering limited hardware resource and higher precision requirement, a NCO with a new hybrid scheme of both LUT and CORDIC algorithms is adopted. This scheme combines the respective advantages of fast access and power efficiency of reasonably sized LUTs and of in principle arbitrary precision obtainable from a rigorous iteration algorithm [5] [6].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Digital Up Converter for Homenet

Cui

Yu²,

Sheng³

et al.

2005 IEEE Conference on Electron Devices and Solid-State Circuits

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Based on the classical system design flow, a custom digital up converter (DUC) IP is designed and implemented for Homenet system. At the system level, DUC behavior model is constructed and DUC system architecture, spectra distribution scheme and circuit parameters are confirmed with system modeling tool MATLAB. At the circuit level, the main function modules such as interpolator and numerically controlled oscillators (NCO) and so on are designed and implemented. Considering the limited hardware resources and performance specification, a large number of optimizing technologies and algorithm are adopted. At last, Homenet system verification flat including our custom digital up converter system is realized with Xilinx Virtexll XC2V1000-4FG256 FPGA.

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FPGA-efficient phase-to-I/Q architecture

Janiszewski

Meuth

Hoppe

IEEE International SOC Conference, 2004. Proceedings.

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Precision and performance of numerically controlled oscillators with hybrid function generators

Cited by 3 publications

References 11 publications

Pipeline-efficient hybrid vectoring implementation

Pipeline-efficient hybrid vectoring implementation

Design and Implementation of Digital Up Converter for Homenet

FPGA-efficient phase-to-I/Q architecture

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