Precise scheduling of mixed-criticality tasks by varying processor speed

Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information

“…In this subsection, we describe the RTA for our scheduling algorithm, which considers the following assumption: Assumption: We assume that the WCET and the processor speed has a linear relationship [13], i.e., if τ i starts executing on a processor (with C lo i ) with a degraded speed s lo , it will take C lo i /s lo time units to finish execution. Recall that under the lo-criticality mode, all the lo-and hi-criticality tasks execute at an energy-conserving speed, i.e., s lo .…”

“…All these papers assumed that all lo-criticality tasks are dropped after a modeswitch. The recent work in [13] proposed the technique to provide a full-service guarantee to all lo-criticality tasks (even after a mode switch) and most related to this work. However, it is also based on the pessimistic assumption that all the tasks will execute up to their WCET (at the corresponding system criticality level) and did not consider the probabilistic information to derive the lo-criticality execution time thresholds.…”

“…the lo-criticality tasks may result in severe performance loss and it violates the task independence requirements for safetycritical systems [21]. A recent work by Bhuiyan et al [13] handled the precise scheduling of MC systems, where full service is provided to all tasks under both the pessimistic and optimistic assumptions. They incorporated the dynamic voltage frequency scaling (DVFS) scheme to the precise scheduling strategy and derived the energy-aware CPU speed to execute in normal mode.…”

“…Our Contribution. Existing works aimed at minimizing energy consumption at lo-criticality mode, but considered a pessimistic assumption that all the tasks execute up to their WCET, at their respective criticality levels [13]. Since a task rarely needs to execute up to its WCET, we integrate the probabilistic based prediction strategy and the DVFS scheme to the precise scheduling of MC tasks.…”

F2vd

“…The criticism mainly arises from the impreciseness of the execution of less critical functionalities, as a result of their execution budget reduction in hi-mode. A recent paper [12] suggested a novel precise MC scheduling framework, where all tasks receive full execution budget under all circumstances. By following the MC-Fluid framework [6,28] and leveraging the dynamic voltage and frequency scaling (DVFS) technique, the processor execution speed is minimized under normal circumstances, while resumed to full speed when there is task overrun (characterized as a mode switch).…”