Pre-synthesis Optimization of Multiplications to Improve Circuit Performance

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

“…Their method does explore a restricted set of architectures, but it is unclear from the paper how it is done. Partitioning of multiplication operations into smaller multiplications and additions has also been studied in [18] as a presynthesis optimization step in high level synthesis with a view to decrease the circuit delay. However, it does not make use of Karatsuba-Ofman algorithm for partitioning the multiplication operations.…”

“…Algorithm 2 abstracts this hardware design viewpoint and automates it for HLS. Perform a Depth First Search (DFS) with constant value node as root node to find its successor node (5) If the second input to successor node is labeled a variable, store the variable identity and the constant in a hash table: H(MUL) (6) EndIf (7) EndIf (8) End BFS (9) Identity (ID) = 0 (10) For each multiplication node (11) Check if successor node, SN is addition or subtraction else Step 9 (12) Check if successor node SNN of SN is addition or subtraction (13) If (11) is TRUE (14) Check if second operand source of SNN is a MUL node (15) If (13) is TRUE (16) Collect all nodes in 9, 10, 11, and 13 as a partial graph (17) SN = SNN (18) Repeat 11 to 16 until (11) or (13) returns FALSE (19) Chain Detected = Yes (20) Length of chain = Number of ADD/SUB nodes (21) Chain ID = ID + 1 (22) EndFor (23) Remove from H(MUL) all MUL nodes collected in Step 15.…”

Intelligent high level synthesis for customization on reconfigurable platforms

“…Mapping to DSP blocks on Xilinx FPGAs have been investigated in [206] and on both Xilinx and Altera DSP blocks in [207] with the aim to reduce the number of DSP blocks needed when the basic multiplication would involve more than one DSP resource. Their work has relied on the Karatsuba-Ofman algorithm [208] Partitioning of multiplication operations into smaller multiplications and additions has also been studied in [211] as a pre-synthesis optimization step in high level synthesis with a view to decreasing the circuit delay. However, it does not make use of Karatsuba-Ofman algorithm for partitioning the multiplication operations.…”