Practical Temporal Prefetching With Compressed On-Chip Metadata

Wu, Hao; Nathella, Krishnendra; Pabst, Matthew; Sunwoo, Dam; Jain, Anshul; Lin, Calvin

doi:10.1109/tc.2021.3065909

Cited by 2 publications

(1 citation statement)

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“…Temporal prefetchers [3], [13], [28] can predict memory access patterns based on temporal locality, especially recurring access patterns that arise when iterating over data structures, so as to reduce data access latency. MISB [13] utilizes the access patterns of irregular data structures, such as linked lists, trees, and graphs to predict future data access and fetch data to cache.…”

Section: Hardware Prefetchersmentioning

confidence: 99%

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

Fang

Cai

et al. 2023

Preprint

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Modern processors employ data prefetchers to alleviate the impact of long memory access latency. However, current prefetchers are designed for specific memory access patterns, which perform poorly on mixed applications with multiple memory access patterns. To address these issues, RL-CoPref, a reinforcement learning (RL)-based coordinated prefetching controller for multiple prefetchers, is proposed in this paper. RL-CoPref takes diverse program context information as the input, learns to maximize cumulative rewards, and evaluates prefetch quality based on prefetch hits/misses and memory bandwidth utilization. It can dynamically adjust the prefetch activation and prefetch degree, enabling multiple prefetchers to complement each other on mixed applications. Our extensive evaluation, utilizing the ChampSim simulator, demonstrates that RL-CoPref can effectively adapt to various workloads and system configurations, optimizing prefetch control. On average, RL-CoPref achieves 76.15% prefetch coverage, having 35.50% IPC improvement, outperforming state-of-the-art individual prefetchers by 5.91%−16.54% and outperforming SBP, a state-of-the-art (non-RL) prefetch controller, by 4.64%.

show abstract

Section: Hardware Prefetchersmentioning

confidence: 99%

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

Fang

Cai

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

RL-CoPref: a reinforcement learning-based coordinated prefetching controller for multiple prefetchers

Yang,

Fang,

et al. 2024

J Supercomput

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Modern processors employ data prefetchers to alleviate the impact of long memory access latency. However, current prefetchers are designed for specific memory access patterns, which perform poorly on mixed applications with multiple memory access patterns. To address these issues, RL-CoPref, a reinforcement learning (RL)-based coordinated prefetching controller for multiple prefetchers, is proposed in this paper. RL-CoPref takes diverse program context information as the input, learns to maximize cumulative rewards, and evaluates prefetch quality based on prefetch hits/misses and memory bandwidth utilization. It can dynamically adjust the prefetch activation and prefetch degree, enabling multiple prefetchers to complement each other on mixed applications. Our extensive evaluation, utilizing the ChampSim simulator, demonstrates that RL-CoPref can effectively adapt to various workloads and system configurations, optimizing prefetch control. On average, RL-CoPref achieves 76.15% prefetch coverage, having 35.50% IPC improvement, outperforming state-of-the-art individual prefetchers by 5.91–16.54% and outperforming SBP, a state-of-the-art (non-RL) prefetch controller, by 4.64%.

show abstract

Practical Temporal Prefetching With Compressed On-Chip Metadata

Cited by 2 publications

References 44 publications

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

RL-CoPref: a reinforcement learning-based coordinated prefetching controller for multiple prefetchers

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