Practical Implementation of Lattice QCD Simulation on SIMD Machines with Intel AVX-512

Abstract

We investigate implementation of lattice Quantum Chromodynamics (QCD) code on the Intel AVX-512 architecture. The most time consuming part of the numerical simulations of lattice QCD is a solver of linear equation for a large sparse matrix that represents the strong interaction among quarks. To establish widely applicable prescriptions, we examine rather general methods for the SIMD architecture of AVX-512, such as using intrinsics and manual prefetching, for the matrix multiplication. Based on experience on the Oakforest-PACS system, a large scale cluster composed of Intel Xeon Phi Knights Landing, we discuss the performance tuning exploiting AVX-512 and code design on the SIMD architecture and massively parallel machines. We observe that the same code runs efficiently on an Intel Xeon Skylake-SP machine.

Object-Oriented Implementation of Algebraic Multi-grid Solver for Lattice QCD on SIMD Architectures and GPU Clusters

“…] which is written in C++ based on the object-oriented design. Bridge++ has been used to investigate a recipe of tuning on Intel AVX-512 architectures [21,22].…”

“…For the smaller local volume case, the domain-decomposed operator is faster than the full operator as expected from the absence of communications. The tuning described in [22] for full operator works quite efficiently for a larger local volume so that its performance exceeds Table 1. Elapsed time for the multi-grid solver.…”

“…The implementation of the fine grid operators inherits the previous works [21,22] and uses the L2 prefetch in the full operator D. Although it has been tuned for D, the same prefetching pattern is used in the SAP operator.…”

General purpose lattice QCD code set Bridge++ 2.0 for high performance computing

“…This requires that the lattice size in x-direction must be a multiple of 8. The details of the tuning with the AVX-512 instruction set were presented in [7]. For Armv8.2-A-SVE, we adopt a different packing: as depicted in the right panel of Fig.…”

“…Recent supercomputers, however, adopt a variety of architecture: multi-core parallel machines with wide SIMD (A64FX and Intel processors), and clusters with accelerator devices such as GPUs, PEZY-SC, and vector processors (NEC SX-Aurora). Soon after the first public release of Bridge++ in 2012 [2], we had started to investigate possible extensions of our code to exploit these new architectures while keeping the readability and portability, as well as to develop tuning techniques for them [3,4,5,6,7,8]. Recently we have constructed a framework to incorporate the tuned codes as an alternative part to the previously developed Bridge++ code, and decided to release it as version 2.0.…”