Practical implementation of digital down conversion for wideband direction finder on FPGA

Obradovic, Vuk; Okiljevic, Predrag; Kozić, Nadica; Ivković, Dejan

doi:10.5937/str1604040o

Cited by 12 publications

(1 citation statement)

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“…The implementation schemes controlled the spurious-free dynamic range (SFDR). Again, the authors in V. Obradović et al [7] discussed a flexible DDC architecture for wideband direction finder. The DDC was tested on Xilinx Kintex-7 using Xilinx IP cores to implement the filters chain.…”

Section: Introductionmentioning

confidence: 99%

Area and power-efficient reconfigurable digital down converter on FPGA

Datta

Dutta

2022

FACTA U EE

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This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

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Section: Introductionmentioning

confidence: 99%