Practical application of aerial imaging mask inspection for memory devices

Baik, Hyun Joo; Chung, Dong Hoon; Kim, Yong Hoon; Cho, Han Ku; Sagiv, Amir; Mangan, Shmoolik; Parizat, Ziv; Park, Eun Young; Brami, Yaniv; Bernstein, Dana

doi:10.1117/12.793057

Cited by 3 publications

(2 citation statements)

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“…In contrast, the constraints to which aerial defect detection is subject are likely much less stringent. As shown in [7], it is the 1 st order interaction between the electric fields due to the pattern and defect, respectively, that gives rise to the defect signal under aerial imaging optical conditions. Loosely speaking,…”

Section: Defect Inspection With Smo Illuminationmentioning

confidence: 99%

Aerial imaging for source mask optimization: mask and illumination qualification

et al. 2009

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As the semiconductor industry moved to 4X technology nodes and below, low-k 1 ArF lithography approached the theoretical limits of single patterning resolution, a regime typically plagued by marginally small process windows. In order to widen the process window bottleneck, projection lithography must fully and synergistically employ all available degrees of freedom. The holistic lithography source mask optimization (SMO) methodology aims to increase the overall litho performance and achieve a robust process window for the most challenging patterns by balancing between the mask and illumination source design influences. The typical complexity of both mask and illumination source that results from a generic SMO process exceeds the current norm in the lithographic industry. In particular, the SMO literature reports on masks that fully operate as diffractive optical elements, with features that have little resemblance to the final wafer-level pattern. Additionally, SMO illumination sources are characterized by parametric or pixelated shapes and a wide range of transmission values. As a consequence of the new mask and source designs, qualifying the mask for printing and non-printing defects and accurate assessment of critical dimensions becomes one of the main mask inspection challenges. The aerial imaging technologies of Applied Material's Aera2™ mask inspection tool provide enabling solutions by separating out only the defects that matter and accurately measures aerial imaging critical dimensions. This paper presents the latest numerical and experimental SMO mask qualifications research results performed at Applied Materials with a mask containing two-dimensional DRAM production structures.

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Section: Defect Inspection With Smo Illuminationmentioning

confidence: 99%

Aerial imaging for source mask optimization: mask and illumination qualification

et al. 2009

Self Cite

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“…The Applied Materials AERA™ inspection system is an aerial-image-based mask-inspection system. [84][85][86][87][88][89][130][131][132][133][134] KLA has introduced WPI/API to examine the impact on the wafer as a way to filter defects on mask. [135][136][137] Brion Technologies and NuFlare developed off-line lithography simulation software for the NuFlare mask inspection system.…”

Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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