Practical advances in asynchronous design and in asynchronous/synchronous interfaces

Brunvand, E.; Nowick, S.; Yun, K.

doi:10.1109/dac.1999.781284

Cited by 8 publications

(8 citation statements)

References 65 publications

(5 reference statements)

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“…1 In a synchronous state machine, the actual bit patterns used to distinguish the states (the state vector) are irrelevant from the point of view of the behavior of the machine. The state-state transitions are dictated by the "glue logic" and orchestrated by the clock.…”

Section: A Optimization-measure Of Goodnessmentioning

confidence: 99%

A behavioral synthesis system for asynchronous circuits

Sacker

Brown

Rushton

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional units); and 3) binding (the mapping of the functional units onto physical cells). Optimization is usually achieved by intelligent manipulation of these three steps in some way. Key to the operation of such a system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronizing clock. The maximum clock speed is dictated by the slowest time slot. (This is the timeslot containing the longest combinational logic delay.) Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of "ready" and "acknowledge," the control graph becomes a disjoint set of single-state machines-it effectively disappears, with the consequence that the timeslot-timeslot transitions become self controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes selftiming: asynchronous. This paper describes a behavioral asynchronous synthesis system based on this concept that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level description). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed.

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Section: A Optimization-measure Of Goodnessmentioning

confidence: 99%

A behavioral synthesis system for asynchronous circuits

Sacker

Brown

Rushton

et al. 2004

IEEE Trans. VLSI Syst.

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“…Adding two-phase (transition signaling logic) to four-phase (level sensitive logic) converters to each microoperation may solve the problem since two-phase dependency graphs can be easily mapped onto two-phase control circuits. 1 Although we used to call asynchronous circuits using return-to-zero handshakes two-phase or four-cycling, we call them four-phase in this paper.…”

Section: Introductionmentioning

confidence: 99%

“…There have been a lot of works done for asynchronous design [1] including synthesis methods of controllers [2,3,4], and pipeline controller design [5,6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs

Kagotani

Okamoto

Nanya

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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-We propose a method of synthesizing pipeline controllers as four-phase asynchronous circuits from specifications described as two-phase dependency graphs. Pipeline twophase dependency graphs are transformed into four-phase ones by applying a transformation rule to each simple loop in the graphs. Four-phase dependency graphs are easily mapped onto four-phase asynchronous control circuits. We also discuss some simplification of four-phase dependency graphs.

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“…FIFO queues have the advantage that the inter-domain synchronization penalty can be hidden whenever the FIFO is neither full nor empty. The mechanism by which this is achieved and the precise definitions of Full and Empty are described in Section 4.1 and are similar to mixed clock FIFOs proposed by others [3,5,6,7,21]. The disadvantage of FIFO queue structures is that they can only be used where strict First-In-First-Out queue organization is applicable.…”

Section: Domain Interface Circuitsmentioning

confidence: 99%