PR-STM: Priority Rule Based Software Transactions for the GPU

Abstract

In this paper we describe an implementation of a software transactional memory library for the GPU written in CUDA. We describe the implementation of our transaction mechanism which features both tentative and regular locking along with a contention management policy based on a simple, yet effective, static priority rule called Priority Rule Software Transactional Memory (PR-STM ). We demonstrate competitive performance results in comparison with existing STMs for both the GPU and CPU. While GPU comparisons have been studied, to the best of our knowledge we are the first to provide results comparing GPU based STMs with a CPU based STM.

HeTM: Transactional Memory for Heterogeneous Systems

“…A second relevant observation is that architectural differences of CPUs and (discrete) GPUs have a great impact on their programming models and, as such, HeTM systems should keep these aspects into account to attain high efficiency. One key issue is that, differently from CPUs, where transactions are typically executed individually, in GPUs it is desirable to execute transactions in relatively large batches [50], [7], as this allows for: i) amortizing the latency of transactions' activation; ii) enhancing throughput when transferring to/from the GPU the inputs/output required/produced by transactions' execution; iii) improving resource utilization on modern GPUs.…”

“…Supported libraries. Currently, SHeTM supports three TM implementations: two on the CPU side -TinySTM [15] and Intel's TSX [29], implemented respectively in software and hardware -and one on the GPU side, namely PR-STM [50].…”

“…As mentioned, the literature in the area of TM has elaborated a plethora of design, exploring both hardware and software implementations. The majority of the existing literature has focused on investigating TM implementations for CPUs, although a number of TM systems for GPUs [18], [27], [57], [50] have been explored of late. In this area, a relevant related work is the recent APUTM [54], which addressed the problem of implementing a STM for integrated GPUs.…”