PQEMU: A Parallel System Emulator Based on QEMU

Ding, Jiun-Hung; Chang, Pyung Hun; Hsu, Wei-Chung; Chung, Yeh‐Ching

doi:10.1109/icpads.2011.102

Cited by 35 publications

(16 citation statements)

References 9 publications

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“…the Linux implementation of the spin lock functions, and are designed to keep as short as possible the lifespan of the EMR in order to minimize the number of conflicts. [Wang et al 2011] and [Ding et al 2011] could have been two candidates for comparison against the presented work, however, only the upstream version of QEMU (whose source code is available at [4]) will be taken into account. In fact, QEMU has been significantly evolving over the last years and as such, results from these previous attempts would be considered deprecated and outdated.…”

Section: Resultsmentioning

confidence: 99%

“…RELATED WORK There have been already some attempts to make QEMU multi-threading in the past, all of them had to address the problem of atomic instruction translation. PQEMU [Ding et al 2011] implemented the translation of ARM's LDREX and STREX instructions enclosing their actual memory access in a mutex. This solution, although capable of serializing all the overlapping atomic accesses, is unable to emulate completely the LL/SC semantic since it does not solve the ABA problem.…”

Section: Results Analysismentioning

confidence: 99%

See 1 more Smart Citation

Atomic Instruction Translation Towards A Multi-Threaded QEMU

Rigo¹,

Spyridakis²,

Raho³

2016

ECMS 2016 Proceedings Edited by Thorsten Claus, Frank Herrmann, Michael Manitz, Oliver Rose

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In the context of system emulation, the sophistication of the emulator usually grows with the complexity of the target system model. Particularly, emulating precisely a certain CPU architecture can introduce many challenges that have to be properly explored and somehow solved to reach an accurate emulation of the target system.In this paper we present an implementation design of ARM atomic instructions for a multi-threaded version of QEMU (the Quick EMUlator), currently under development [1].To prove the correctness and performance of such an implementation, some tests have been performed showcasing a high degree of accuracy and fidelity of the emulated instructions. While this paper does not cover all possible guest architectures that QEMU supports, the described new approach results in a reliable infrastructure that eventually can address all target architectures in QEMU.

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Section: Resultsmentioning

confidence: 99%

Section: Results Analysismentioning

confidence: 99%

Atomic Instruction Translation Towards A Multi-Threaded QEMU

Rigo¹,

Spyridakis²,

Raho³

2016

ECMS 2016 Proceedings Edited by Thorsten Claus, Frank Herrmann, Michael Manitz, Oliver Rose

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“…Parallel emulators (e.g. PQEMU [38], COREMU [39], Parallel Mambo [40] , and Parallel Embra [41]) and simulators (e.g. FastMP [42], SlackSim [43], Wisconsin Wind Tunnel Simulators (WWT) [44,45], CMPSim [46], ZSim [13], MARSS [6], SimFlex [47], GEMS [26], COTSon [23], Graphite [11], Sniper [12,48] and BigSim [10]) enhance the performance of simulation (in terms of simulation speed) by dividing and distributing the simulation workload across multiple cores on multiple host machines.…”

Section: Terminology and Classificationsmentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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“…Instruction-set simulation is an active field of research, and a large number of techniques for the efficient implementation of either user mode or full system simulators has been published, for example, Böhm et al [2011], Böhm et al [2010], Witchel and Rosenblum [1996], Binkert et al [2011], Patel et al [2011], Sandberg et al [2015], Yourst [2007], Bellard [2005], Ding et al [2011], Magnusson et al [2002], Qin and Malik [2003], and AMD Developer Central [2010]. In Table III, we provide an overview of well-known simulators and their capabilities and implementation techniques.…”

Section: Related Workmentioning

confidence: 99%

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Spink

Wagstaff

Franke

2016

ACM Trans. Archit. Code Optim.

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Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by all major processor architectures, including Intel, ARM, PowerPC, and MIPS, these extensions are targeted at virtualization of the same architecture, for example, an x86 guest on an x86 host system. Existing techniques for cross-architecture virtualization, for example, an ARM guest on an x86 host, still incur a substantial overhead for CPU, memory, and I/O virtualization due to the necessity for software emulation of these mismatched system components. In this article, we present a new hardwareaccelerated hypervisor called CAPTIVE, employing a range of novel techniques that exploit existing hardware virtualization extensions for improving the performance of full-system cross-platform virtualization. We illustrate how (1) guest memory management unit (MMU) events and operations can be mapped onto host memory virtualization extensions, eliminating the need for costly software MMU emulation, (2) a block-based dynamic binary translation engine inside the virtual machine can improve CPU virtualization performance, (3) memory-mapped guest I/O can be efficiently translated to fast I/O specific calls to emulated devices, and (4) the cost for asynchronous guest interrupts can be reduced. For an ARM-based Linux guest system running on an x86 host with Intel VT support, we demonstrate application performance levels, based on SPEC CPU2006 benchmarks, of up to 5.88× over state-of-the-art QEMU and 2.5× on average, achieving a guest dynamic instruction throughput of up to 1280 MIPS (million instructions per second) and 915.52 MIPS, on average.

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PQEMU: A Parallel System Emulator Based on QEMU

Cited by 35 publications

References 9 publications

Atomic Instruction Translation Towards A Multi-Threaded QEMU

Atomic Instruction Translation Towards A Multi-Threaded QEMU

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Hardware-Accelerated Cross-Architecture Full-System Virtualization

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