POWER5 system microarchitecture

Sinharoy, Balaram; Kalla, R.; Tendler, Joel M.; Eickemeyer, Richard J.; Joyner, J. B.

doi:10.1147/rd.494.0505

Cited by 207 publications

(186 citation statements)

References 8 publications

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“…This timing model has been validated to be cycle-accurate with respect to Power5 hardware within a 2% margin of error averaged across a suite of benchmarks [25]. The publicly available attributes of the machine are detailed in prior work [21]. Most pertinent to this research is its 8-way set associative 64KB instruction cache, with 128 byte cache blocks.…”

Section: Experimental Methodologymentioning

confidence: 99%

Call-chain Software Instruction Prefetching in J2EE Server Applications

Nagpurkar¹,

Cain²,

Serrano³

et al. 2007

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

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We present a detailed characterization of instruction cache performance for IBM's J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks on WebSphere, we find that instruction cache misses cause a 12% performance penalty on currentgeneration Power5-based multiprocessor systems. To mitigate this performance loss, we describe a new call-chain based algorithm for inserting software prefetch instructions, and evaluate its potential for improved instruction cache performance. The performance of this algorithm depends on the selection of several independent parameters which control the distance and number of prefetches inserted for a particular method. We select these parameters through characterization of the WebSphere applications, and ultimately find that our call-chain based insertion algorithm achieves significant reduction in instruction cache miss rate for Java methods.

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Section: Experimental Methodologymentioning

confidence: 99%

Call-chain Software Instruction Prefetching in J2EE Server Applications

Nagpurkar¹,

Cain²,

Serrano³

et al. 2007

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

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“…The reverse engineering process took a lot of time and efforts. The extracted MCM POWER4 chip is scaled into 45nm technology as POWER4 chip is built on the old 90nm technology (Sinharoy et al, 2005). There are two DTM evaluation index implementations presented in this section.…”

Section: Simulation Resultsmentioning

confidence: 99%

Multi-Core CPU Air Cooling

Elsawaf¹,

El-Shafei²,

Fahmy³

2011

Heat Transfer - Engineering Applications

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“…These CMOS compatible technologies have been used both in the industry and the academia to implement processor caches. For instance, in some modern microprocessors [13], [27], [28] SRAM technology is employed in L1 processor caches while eDRAM cells are used to allow huge storage capacity in last level caches. Regarding academia, some recent works [29], [32] mingle these technologies in several cache levels.…”

Section: B Dealing With Scalability In Future Cmpsmentioning

confidence: 99%

PS directory: a scalable multilevel directory cache for CMPs

et al. 2014

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Abstract-As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures in order to scale in terms of performance, power, and area. Systems that use directory information for coherence purposes are currently the most scalable alternative. This paper studies the important differences between the directory behavior of private and shared blocks, which claim for a separate management of both types of blocks at the directory. We propose the PS directory, a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namely Shared cache, and uses a larger and slower second-level Private cache to track the large amount of private blocks. Entries in the Private cache do not implement the sharer vector, which allows important silicon area savings.Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private cache, which in turn brings energy savings. Experimental results for a 16-core CMP show that, compared to a conventional directory, the PS directory improves performance by 14% while reducing silicon area and energy consumption by 34% and 27%, respectively. Also, compared to the state-of-the-art Multi-Grain Directory, the PS directory apart from increasing performance, it reduces power by 18.7%, and provides more scalability in terms of area.

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POWER5 system microarchitecture

Cited by 207 publications

References 8 publications

Call-chain Software Instruction Prefetching in J2EE Server Applications

Call-chain Software Instruction Prefetching in J2EE Server Applications

Multi-Core CPU Air Cooling

PS directory: a scalable multilevel directory cache for CMPs

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