Power-yield optimization in MPSoC task scheduling under process variation

Momtazpour, Mahmoud; Sanaei, Esmaeel; Goudarzi, Maziar

doi:10.1109/isqed.2010.5450497

Cited by 12 publications

(12 citation statements)

References 12 publications

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“…This work extends our previous work [11] in the field of MPSoC task scheduling and binding for power maximization by adding the ability of switching between different power modes to each processor. It can be shown that by adding the flexibility of dynamically choosing different power modes for each processor to task scheduling process, total power of an MPSoC is effectively reduced.…”

Section: Introductionmentioning

confidence: 68%

“…Note that to find the dynamic power of each task, the allocated processor's power should be determined by examining the first part of the current chromosome (Algorithm 3, line 3). Then, the idle energy consumption is determined for all resources in the MPSoC as the sum of product of each processor's idle power and the sum of its idle intervals (Algorithm 3, line [9][10][11][12][13][14]. It is assumed that the processors only consume leakage power in their idle intervals, because in idle mode all internal clocking are stopped.…”

Section: Proposed Task Scheduling and Power Mode Selection Algorithmmentioning

confidence: 99%

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Variation-aware task scheduling and power mode selection for MPSoC power optimization

Momtazpour¹,

Goudarzi²,

Sanaei³

2010

2010 15th CSI International Symposium on Computer Architecture and Digital Systems

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Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by simulating the algorithm with two different statistical analysis methods called Monte Carlo and Event-Reference-Table-based method. We have shown that by considering both leakage and frequency variation during the simultaneous selection of task scheduling and power mode switching policies, our algorithm achieves significant improvement over conventional methods.

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Section: Introductionmentioning

confidence: 68%

Section: Proposed Task Scheduling and Power Mode Selection Algorithmmentioning

confidence: 99%

Variation-aware task scheduling and power mode selection for MPSoC power optimization

Momtazpour¹,

Goudarzi²,

Sanaei³

2010

2010 15th CSI International Symposium on Computer Architecture and Digital Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…In [4], the authors optimize the energy consumption in multiprocessor systems considering process variation but their approach is not a statistical optimization and they have considered the effect of variation as known values. In [5] the employed optimization algorithm is a meta-heuristic approach, which cannot guarantee convergence to the optimal solution while their execution time is also rather high. In this work we present an Integer Linear Programming (ILP) formulation for the problem of statistical task scheduling on an MPSoC and demonstrate its advantages to traditional worst-case based techniques by providing experimental results on public domain benchmarks [6].…”

Section: Introductionmentioning

confidence: 99%

A variation and energy aware ILP formulation for task scheduling in MPSoC

Ghorbani

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-onChips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditional approaches try to improve the worst-case value for energy of a system whereas statistical optimizations are more recently employed to optimize the energy yield under a given energy constraint. In this work, we have formulated statistical optimization by integer linear programming. Our experimental results on E3S benchmark suite show that statistical approach for task scheduling can achieve up to 22% improvement over the conventional approach in terms of energy yield and demonstrate this superiority is improved when the amount of variation increases.

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“…They further extended their work to considered not only performance differences of multiple cores, but also physical link differences in NoC as well. Momtazpour et al [15] considered a similar task graph mapping problem on a multi-core NoC architecture, with the goal to maximize the percentage of manufactured chips that can meet power constraints for a given application. These statistical approaches try to optimize results in a probabilistic manner.…”

Section: Introductionmentioning

confidence: 99%

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Wang

Quan

Ren

et al. 2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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As transistor's feature size continues to scale down into the deep sub-micron domain, IC chip performance variation caused by manufacturing process becomes un-negligible and can cause significant discrepancies between an application's nominal design and its actual realization on individual manycore platforms. In this paper, we study the problem on how to reduce the total schedule length of a task graph when realizing its nominal design on individual Network-on-Chip(NoC) based many-core platform with faulty cores. Different from traditional approaches to re-define the mapping/scheduling decisions in the nominal design, our methods judiciously mirror the physical architecture of each individual platform to the logical platform, based on which the nominal design is conducted. To facilitate the phyical/logic architecture virtualization, we develop a performance metric based on the opportunity cost, a concept borrowed from the economics field. Three virtualization heuristics are presented in this paper. Our experimental results show that the proposed approach can achieve up to 30% with an average 15% performance improvement by taking advantage of the heterogeneity of each individual platform.

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Power-yield optimization in MPSoC task scheduling under process variation

Cited by 12 publications

References 12 publications

Variation-aware task scheduling and power mode selection for MPSoC power optimization

Variation-aware task scheduling and power mode selection for MPSoC power optimization

A variation and energy aware ILP formulation for task scheduling in MPSoC

Topology Virtualization for Throughput Maximization on Many-Core Platforms

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