Power supply noise simulation considering dynamic effect of on-chip current

Zhou, Yaping; Dhong, S.H.; Nishino, Y.; Harvey, Paul; Mandrekar, R.; Gervais, G.; Criscolo, N.

doi:10.1109/epep.2006.321198

Cited by 5 publications

(18 citation statements)

References 4 publications

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“…In general, there should not be any difference in the value of exponent between logic and clock circuits since both were designed using the same CMOS process and thus one should expect the same exponent if there is any physics associated with the exponents number, B. In general, this paper [9] determined experimentally all the possible dc current that can be drawn by the device (Power PC) in dc state and no time-dependent behavior was discussed.…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 98%

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 98%

“…Dutta and Kumar [9] do not describe any time-dependent behavior of shoot-through current. The effect of leakage current due to the variation of power supply voltage, as shown in [9], has an effect of variable damping in PDN. But the effect of ac noise on the first voltage drop (for any given voltage V CC and current ramp) will have very small impact due to this variable resistance on leakage current.…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 98%

“…The authors in [9] have shown that the logic dc current can be described as AV B , where B is an exponent and for power PC processors they found that the coefficient B = 1.56. They explained that in terms of shoot-through current of a CMOS gate.…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 99%

“…This helps while one superimposes noise from different times, from different current ramps, and from the first noise curve, which is decaying as a function of time. The exponent of a dc current through clock circuit in [9] was measured to be 1.24 and that is different from logic and according to the authors that can be due to two different circuits in their given processor. In general, there should not be any difference in the value of exponent between logic and clock circuits since both were designed using the same CMOS process and thus one should expect the same exponent if there is any physics associated with the exponents number, B.…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 99%

See 4 more Smart Citations

Method to Simulate Rise Time of Current Drawn by a Microprocessor

Bhattacharyya

Baral

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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We have developed a new method to simulate the effective rise time of current drawn by each cell in a microprocessor so that the total noise is consistent with values measured at the power and ground reference points inside the die. Normally, the measured values are much smaller than simulated values. In this paper, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile which was used for noise estimation. The model utilizes a realistic jitterbased distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp. The practical model developed in this paper is useful for optimizing the cost and performance of microprocessors.Index Terms-Average power drawn by CMOS device, current ramp generation, microprocessor currrent simulation, noise simulation, power delivery, power delivery network (PDN), rise time of current, stastical process for power delivery.

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Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 98%

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 98%