Power Scalable Radio Receiver Design Based on Signal and Interference Condition

Dwivedi, Satyam; Amrutur, Bharadwaj; Bhat, Navakanta

doi:10.3390/jlpea2040242

Cited by 9 publications

(7 citation statements)

References 17 publications

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“…New solutions to save power on the RF communications have also been developed at MAC or network level such as energy efficient protocols where the transmission data rate can vary when the sensitivity of the node is reduced [5]. A low power adaptive digital baseband for standard IEEE 802.15.4 through a variation of word length and sampling frequency is presented in [6]. However, these approaches address mainly digital baseband.…”

Section: State Of the Art Adaptive Receivermentioning

confidence: 99%

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

Zaini-Desevedavy

Hameau

Taris

et al. 2018

JLPEA

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This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm 2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.

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Section: State Of the Art Adaptive Receivermentioning

confidence: 99%

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

Zaini-Desevedavy

Hameau

Taris

et al. 2018

JLPEA

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“…The paper [9] presents a baseband digital receiver design that changes its sampling frequency (fs) and word length based on interference detection and signal quality estimation. Adaptive technique was used to reduce power by choosing optimum word length for given error conditions.…”

Section: Introductionmentioning

confidence: 99%

An optimum ADC output word length selection for low power communication architectures

Manga

Latha

2013

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Low power Very Large Scale Integration (VLSI) design for communication applications is key technology area, driving current mobile communication and wireless networking sectors. The decades of research in Complementary Metal Oxide Semiconductor (CMOS) VLSI technologies could achieve low power design procedures at transistor and circuit level design. To further achieve low power, the researchers are looking at system level design by adopting suitable algorithms and architectures. This paper illustrates one of the power optimization techniques, by reducing the number of ADC output bits, while considering the system level parameters. The dynamic ADC word length optimizer (WLO) is prototyped in VHDL and verified for its functionality in practical signal conditions. The architecture is synthesized for Spartan-6 SX45T FPGA and results demonstrate maximum clock speeds up to 200 MHz, ensuring its compatibility with all types of wideband communication applications with high speed ADCs. Power analysis carried out with Xpower tool show power reduction by 40%. The proposed WLO is simulated and verified for BPSK demodulation, to achieve the theoretical BER limit of 10 -5 at 9.5 dB SNR value.

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“…The reconfiguration is achieved using an external DAC that controls the supply voltage. Authors in [3] propose a power scalable digital baseband that reduces its power consumption by varying the word length and sampling frequency. In [4] the authors propose to control the power consumption of a receiver by varying the gain and the linearity of a LNA based on the calculated error vector magnitude (EVM).…”

Section: Introductionmentioning

confidence: 99%

Power reconfigurable receiver model for energy-aware applications

Didioui

Bernier

Morche

et al. 2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-This paper presents a reconfigurable receiver model whose purpose is to enable the study of reconfiguration strategies for future energy-aware and adaptive transceivers. This model is based on Figure of Merits of measured circuits. To account for real-life RF interference mechanisms, a link quality estimator is also provided. We show that adapting the receiver performance to the channel conditions can lead to considerable power saving. The models proposed can easily be implemented in a wireless network simulation in order to validate the value of a reconfigurable architecture in real-world deployment scenarios.

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Power Scalable Radio Receiver Design Based on Signal and Interference Condition

Cited by 9 publications

References 17 publications

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

An optimum ADC output word length selection for low power communication architectures

Power reconfigurable receiver model for energy-aware applications

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