Power reduction via separate synthesis and physical libraries

Rahman, Mohammad; Afonso, Ryan; Tennakoon, Hiran; Sechen, Carl

doi:10.1145/2024724.2024868

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…Equation (6) shows the covariance matrix C where n is the number of cells in a path, c ij denotes the covariance between two cells in the data-path and c ii is the covariance of a cell with itself. The covariance between cells is determined by eq.…”

Section: B Convolution Of Probability Distributionsmentioning

confidence: 99%

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Standard cell library tuning for variability tolerant designs

Fabrie¹,

Echeverri²,

Vertreg³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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DisclaimerThis document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem in terms of process controllability, e.g. mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

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Section: B Convolution Of Probability Distributionsmentioning

confidence: 99%

“…The second stage consists of applying the threshold to create a suitable subset of robust cells. The usual tuning of a library creates a subset of cells by excluding complete cells [4,5,6]. In this approach, instead of removing a cell completely, a restriction on the look-up table is imposed.…”

Section: B Convolution Of Probability Distributionsmentioning

confidence: 99%

Standard cell library tuning for variability tolerant designs

Fabrie¹,

Echeverri²,

Vertreg³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

View full text Add to dashboard Cite

show abstract

“…Library tuning as used in [5] is meant to iteratively remove cells from the library to pursue a synthesis speed-up. In paper [6], library tuning is used to reduce power by only using a small subset of cells in the physical design.…”

Section: Introductionmentioning

confidence: 99%

Standard cell library tuning for variability tolerant designs

Fabrie¹,

Echeverri²,

Vertreg³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

View full text Add to dashboard Cite

DisclaimerThis document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain Abstract-In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem in terms of process controllability, e.g. mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

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Cell stack length using an enhanced logical effort model for a library-free paradigm

El-Masry

Al-Khalili

2011

2011 18th IEEE International Conference on Electronics, Circuits, and Systems

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Power reduction via separate synthesis and physical libraries

Cited by 6 publications

References 7 publications

Standard cell library tuning for variability tolerant designs

Standard cell library tuning for variability tolerant designs

Standard cell library tuning for variability tolerant designs

Cell stack length using an enhanced logical effort model for a library-free paradigm

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