Power reduction via near-optimal library-based cell-size selection

Rahman, Mohammad; Tennakoon, Hiran; Sechen, Carl

doi:10.1109/date.2011.5763293

Cited by 19 publications

(12 citation statements)

References 7 publications

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“…Note that the active area, which is the sum of all the transistor widths, corresponds to dynamic power when modulated by the cell activity factors. Although [8] handles activity factors, we have found that assuming all the activity factors are the same yields similar dynamic power results and hence we simply report active area here. From Fig.…”

Section: Fa Selection For Csamentioning

confidence: 63%

“…All of the constituent inverting gates of a FA, for example, SUM-GEN and CARRY-GEN for the type 1 FA, as well as its inverters, are sized independently using [8] to maximize active area reduction for a particular delay target, using the sizes available in a commercial standard cell library. Similarly, the constituents of the XOR2's ( Fig.…”

Section: Csa Constructionmentioning

confidence: 99%

“…3.5 and 3.6. These were generated using [8], a near-optimal library-based (discrete) gate size selection tool, using an industrial 40nm 0.9V process and library, and a nominal wire load model. Note that the active area, which is the sum of all the transistor widths, corresponds to dynamic power when modulated by the cell activity factors.…”

Section: Fa Selection For Csamentioning

confidence: 99%

“…We also deploy a near-optimal discrete (library-based) cell size selection algorithm [8] to minimize the active area needed to achieve any desired delay target. We compare the designs we produce with those produced by the leading commercial synthesis tool (using its best scripts) using cell-based design techniques with nominal wire load models.…”

Section: Introductionmentioning

confidence: 99%

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Power efficient partial product compression

Pan¹,

Wang²,

Song³

et al. 2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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We present a power efficient structure for partial product compression. Since the full-adder cell is a cornerstone for partial product compression, we determined what are the most power efficient full-adder cells for a wide range of delays. We then developed a new delay-based partial product wiring algorithm that uses the faster XOR-based full adder when one input is a gate delay slower in arriving and otherwise uses the more area efficient mirror-based full adder. We show that this new wiring algorithm is more power efficient than the use of only one type of full adder. Compared to the leading automatic synthesis tool, our approach yields better power efficiencies (lower active area for the same delay) as well as lower delays. For the summation of 16 16-bit vectors, our approach reduces active area by 45% for the same delays produced by the leading synthesis tool.

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Section: Fa Selection For Csamentioning

confidence: 63%

Section: Csa Constructionmentioning

confidence: 99%

Section: Fa Selection For Csamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Power efficient partial product compression

Pan¹,

Wang²,

Song³

et al. 2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…While discrete methods avoid the difficult "rounding" problem that continuous methods face, they must directly solve an NP-hard problem [18]. Branch-and-bound [24] and dynamic programming [15,19,22] based approaches can be categorized as discrete.…”

Section: Previous Work On Gate Sizingmentioning

confidence: 99%

Sensitivity-guided metaheuristics for accurate discrete gate sizing

Kahng

Kang

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including V t and L g . Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest, we develop a metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints. Our solutions are evaluated using a rigorous protocol that computes circuit delay with Synopsys PrimeTime. Our implementation Trident outperforms the best-reported results on all but one of the ISPD 2012 benchmarks. Compared to the 2012 contest winner, we further reduce leakage power by an average of 43%.

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