Power, Programmability, and Granularity: The Challenges of ExaScale Computing

Abstract

Reaching an ExaScale computer by the end of the decade, and enabling the continued performance scaling of smaller systems requires significant research breakthroughs in three key areas: power efficiency, programmability, and execution granularity. To build an ExaScale machine in a power budget of 20MW requires a 200-fold improvement in energy per instruction: from 2nJ to 10pJ. Only 4x is expected from improved technology. The remaining 50x must come from improvements in architecture and circuits. To program a machine of this scale requires more productive parallel programming environments -that make parallel programming as easy as sequential programming is today. Finally, problem size and memory size constraints prevent the continued use of weak scaling, requiring these machines to extract parallelism at very fine granularity -down to the level of a few instructions. This talk will discuss these challenges and current approaches to address them.

Efficient Concurrent Search Trees Using Portable Fine-Grained Locality

“…These models enable the analysis of data transfer between two levels of the memory hierarchy. Lower data transfer complexity implies better data locality and, therefore, higher energy efficiency since energy consumption caused by data transfer dominates the total energy consumption [18].…”

“…Unlike conventional locality-aware data structures and algorithms that only concern whether the data is on-chip (e.g., in cache) or not (e.g., in DRAM), new energy-efficient data structures and algorithms must consider data locality in finer-granularity: where on chip the data is 1 . It is estimated that for chips using the 10nm technology, the energy gap between accessing data in nearby on-chip memory (e.g., data in SRAM) and accessing data across the chip (e.g., on-chip data at the distance of 10mm), will be as much as 75x (2pJ versus 150pJ), whereas the energy gap between accessing on-chip data and accessing off-chip data (e.g., data in DRAM) will be only 2x (150pJ versus 300pJ) [18]. Therefore, in order to construct energy efficient software systems, data structures and algorithms should support not only high parallelism but also 1.…”

“…Therefore, in order to construct energy efficient software systems, data structures and algorithms should support not only high parallelism but also 1. In the rest of this paper, the term fine-grained locality is used to refer to data locality on-chip (e.g., data movement between registers, L1-/ L2-caches and last level cache (LLC)) while the term coarse-grained locality is used to refer to data locality off-chip (e.g., data movement between DRAM and LLC) fine-grained data locality [18].…”

Accelerating Applications Using GPUs on Embedded Systems and Mobile Devices

“…They have been adopted in many supercomputers, e.g., Titan, Stampede, and Tianhe-2, mainly for two purposes: (1) improving the performance, and (2) reducing the overall power consumption [1]. As GPUs are becoming ubiquitous in HPC, numerous applications have been ported to GPUbased systems over the past several years, including large scale scientific applications on GPU clusters [2]- [4].…”

BTL: A Framework for Measuring and Modeling Energy in Memory Hierarchies

“…With each level of the memory hierarchy that a data transfer crosses (e.g. between on-chip caches, or from last-level cache to DRAM), the energy consumption of the transfer increases by one order of magnitude or more [4]. The memory hierarchy remains the most important performance factor in computing systems, as latency keeps lagging bandwidth [5].…”