Power optimization of combinational modules using self-timed precomputation

Mota, A. Joao Bosco da; Monteiro, J.; Oliveira, Arlindo L.

doi:10.1109/iscas.1998.706794

Cited by 6 publications

(9 citation statements)

References 4 publications

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“…Another frequently applied technique is the asynchronous design (e.g. [6]), in which signal makes transition only when necessary.…”

Section: Preliminariesmentioning

confidence: 99%

“…Since the dynamic power dissipation in a VLSI is usually introduced by signal transitions in the circuit, many studies have also been carried out to minimize the average power dissipation by reducing switching activities [1] of a given logic circuit. The minimization can be achieved at technology mapping phase [2] and logic design phase [3]- [6]. The major logic design methods for low power include techniques to eliminate glitches [3], [4], to reduce switching activity in normal computation [5], [6].…”

Section: Introductionmentioning

confidence: 99%

“…The minimization can be achieved at technology mapping phase [2] and logic design phase [3]- [6]. The major logic design methods for low power include techniques to eliminate glitches [3], [4], to reduce switching activity in normal computation [5], [6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Retiming-based logic synthesis for low-power

Hsu

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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Power management has become a great concern in VLSI design in recent years. In this paper, we consider the logic level design technique for low power applications. We present a retimingbased optimization method, in which part of the circuit is selected and moved so that it produces logic signals one clock cycle before they are actually applied. If these values can solely determine the output logic level, then the other part of the circuit can be turnedoff to save power. We explore acceptable retimed circuit structures, in which circuit function is not changed. An algorithm is proposed to select the optimal logic block to be retimed. We experiment the low-power circuit structure with some MCNC benchmark circuits, and results indicate an improvement over previous methods. Our method achieves a significant reduction in switching activity, and the reduction can be more than 70% in some case. The required area overhead is very small.

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“…Another frequently applied technique is the asynchronous design (e.g. [6]), in which signal makes transition only when necessary.…”

Section: Preliminariesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Retiming-based logic synthesis for low-power

Hsu

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Retiming-based logic synthesis for low-power

Hsu

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

View full text Add to dashboard Cite

Power management has become a great concern in VLSI design in recent years. In this paper, we consider the logic level design technique for low power applications. We present a retiming-based optimization method, in which part of the circuit is selected and moved so that it produces logic signals one clock cycle before they are actually applied. If these values can solely determine the output logic level, then the other part of the circuit can be turned-off to save power. We explore acceptable retimed circuit structures, in which circuit function is not changed. An algorithm is proposed to select the optimal logic block to be retimed. We experiment the low-power circuit structure with some MCNC benchmark circuits, and results indicate an improvement over previous methods. Our method achieves a significant reduction in switching activity, and the reduction can be more than 70% in some case. The required area overhead is very small.

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Partition-based Retiming and Precomputation for Dynamic Power Reduction

Zhou

Bian

2006

2006 International Conference on Communications, Circuits and Systems

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Power optimization of combinational modules using self-timed precomputation

Cited by 6 publications

References 4 publications

Retiming-based logic synthesis for low-power

Retiming-based logic synthesis for low-power

Retiming-based logic synthesis for low-power

Partition-based Retiming and Precomputation for Dynamic Power Reduction

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