Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing

Ghavami, Behnam; Khosraviani, Mehrshad; Pedram, Hossein

doi:10.1109/dsd.2008.89

Cited by 3 publications

(1 citation statement)

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“…In addition, the framework can be easily extended to include other techniques such as multiple gate oxide assignment. Because of such unique advantages, we have seen recent work that adopted genetic algorithms in power optimization frameworks which used multiple power reduction techniques, for example, the power optimization for asynchronous circuits [34] and FinFET-based combinational logics [35].…”

Section: Power Reduction Techniques and Related Workmentioning

confidence: 99%

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Hung

Xie

Narayanan

et al. 2009

J Sign Process Syst Sign Image Video Technol

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Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V dd assignment, multiple V th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.

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Section: Power Reduction Techniques and Related Workmentioning

confidence: 99%