Power Noise and Near-Field EMI of High-Current System-in-Package With VR Top and Bottom Placements

Xu, Kan; Vaisband, Boris; Sizikov, Gregory; Li, Xin; Friedman, Eby G.

doi:10.1109/tcpmt.2019.2903285

Cited by 10 publications

(2 citation statements)

References 14 publications

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“…Additionally, it is worthwhile to investigate the package voltage regulator (VR) on the SiP placement, as shown in Figure 21 . Both structures contain four components: an IC, a VR, a SiP system, and a decoupling capacitor at the bottom; the red and black lines denote the 12 V and 0.8 V power supply networks, respectively [ 111 ]. The only difference is that Figure 22 a places the VR on the top level and Figure 22 b places the VR on the bottom level.…”

Section: Sip Reliability Optimization Solutionmentioning

confidence: 99%

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

Wang

Yang

et al. 2023

Micromachines

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The system-in-package (SiP) has gained much interest in the current rapid development of integrated circuits (ICs) due to its advantages of integration, shrinking, and high density. This review examined the SiP as its focus, provides a list of the most-recent SiP innovations based on market needs, and discusses how the SiP is used in various fields. Reliability issues must be resolved if the SiP is to operate normally. Three factors—thermal management, mechanical stress and electrical properties—can be paired with specific examples in order to detect and improve package reliability. This review provides a thorough overview of SiP technology, serves as a guide and foundation for the SiP in package reliability design, and addresses the challenges and potential for further development of this kind of package.

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Section: Sip Reliability Optimization Solutionmentioning

confidence: 99%

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

Wang

Yang

et al. 2023

Micromachines

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show abstract

“…SoCs frequently use multiple voltage supply and signal levels inside their various building blocks [15]- [18]. Using multiple technologies operating at various supply voltages within the same SiP can decrease fabrication cost and power consumption [19]- [21]. Emerging technologies using lower supply voltages are highly optimized to improve performance; hence, using them in SiP is advantageous but expensive [22], [23].…”

Section: Introductionmentioning

confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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Synchronization in VLSI

Bairamkulov

Friedman

2022

Graphs in VLSI

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Power Noise and Near-Field EMI of High-Current System-in-Package With VR Top and Bottom Placements

Cited by 10 publications

References 14 publications

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

Synchronization in VLSI

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