Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

Choudhury, Priyanka; Pradhan, Sambhu Nath

doi:10.1007/978-3-642-31494-0_3

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…Let us point out that reducing power consumption, in our case, is not associated with additional overhead costs. The known methods in this area are connected to: (i) the representation of the initial FSM as a network of interacting automata (Chow et al, 1996;Liu et al, 2005), or (ii) the special state assignment (Benini and De Micheli, 1995;Benini et al, 2001;Agrawal et al, 2019), or (iii) the clock gating (Nag et al, 2018) or (iv) the power gating (Pradhan et al, 2011;Choudhury and Pradhan, 2012;Benini et al, 2000). We do not discuss these methods in detail.…”

Section: Resultsmentioning

confidence: 99%

Improving characteristics of LUT-based Mealy FSMs

Barkalov

Titarenko

Mielcarek

2020

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Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.

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Section: Resultsmentioning

confidence: 99%

Improving characteristics of LUT-based Mealy FSMs

Barkalov

Titarenko

Mielcarek

2020

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“…For low-power FSM synthesis, many researchers used decomposition or partition technique to accomplish the task [6,7,31,32]. Choudhury et al realised low power of FSM by simultaneous decomposition and state encoding using genetic algorithm [32]. However, it mainly focused on only dynamic power reduction; Xia et al proposed another low-power FSM partition method.…”

Section: Related Workmentioning

confidence: 99%

“…For low‐power FSM synthesis, many researchers used decomposition or partition technique to accomplish the task [6, 7, 31, 32]. Choudhury et al .…”

Section: Related Workmentioning

confidence: 99%

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MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao

Zhang

Wang

et al. 2018

IET Computers & Digital Techniques

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As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

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Switched Capacitance Minimization

Pal

2014

Low-Power VLSI Circuits and Systems

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Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

Cited by 6 publications

References 8 publications

Improving characteristics of LUT-based Mealy FSMs

Improving characteristics of LUT-based Mealy FSMs

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Switched Capacitance Minimization

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