Power Management Methods: From Specification and Modeling, to Techniques and Verification

Viswanath, Vinod; Muralidhar, Rajeev; Seshadri, Harinarayanan; Narayan, Ananth S.

doi:10.1166/jolpe.2012.1199

Cited by 1 publication

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“…Table 4 shows the different classes of bugs and the new verification techniques required, some of which are hard to verify in pre-silicon (for example, voltage sequencing, due to lack of integrated power delivery models into SOC emulation models) or thermal runways (usually these are usually verified on form factor devices in thermal chambers that simulate different thermal conditions). At a high level, verification can be done at either the gate level, RTL/architectural level or at SOC/system level, as described in detail in [118] and [85]; here we focus on verifying system level energy efficiency. Industrial designs rely heavily on ensuring that once the silicon arrives, power management can be validated as soon as possible, and thermal solutions can be built accurately for the specific form factors in consideration.…”

Section: Verificationmentioning

confidence: 99%

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards

Muralidhar,

Borovica-Gajic,

Buyya

2020

Preprint

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Computing systems have undergone a tremendous change in the last few decades with several inflexion points. While Moore's law guided the semiconductor industry to cram more and more transistors and logic into the same volume, the limits of instruction-level parallelism (ILP) and the end of Dennard's scaling drove the industry towards multi-core chips. More recently, we have entered the era of domain-specific architectures and chips for new workloads like artificial intelligence (AI) and machine learning (ML). These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and increasingly diverse workloads, making systems more complex to architect, design, implement and optimize from an energy efficiency perspective. Energy efficiency has now become a first order design parameter and constraint across the entire spectrum of computing devices. Many research surveys have gone into different aspects of energy efficiency techniques in hardware and microarchitecture across devices, servers, HPC/cloud, data center systems along with improved software, algorithms, frameworks, and modeling energy/thermals. Somewhat in parallel, the semiconductor industry has developed techniques and standards around specification, modeling/simulation and verification of complex chips; these areas have not been addressed in detail by previous research surveys. This survey aims to bring these domains holistically together, present the latest in each of these areas, highlight potential gaps and challenges, and discuss opportunities for the next generation of energy efficient systems. The survey is composed of a systematic categorization of key aspects of building energy efficient systems -(a) specificationthe ability to precisely specify the power intent, attributes or properties at different layers (b) modeling and simulation of the entire system or subsystem (hardware or software or both) so as to be able to experiment with possible options and perform what-if analysis, (c) techniques used for implementing energy efficiency at different levels of the stack, (d) verification techniques used to provide guarantees that the functionality of complex designs are preserved, and (e) energy efficiency standards and consortiums that aim to standardize different aspects of energy efficiency, including cross-layer optimizations.CCS Concepts: • Hardware → Power and energy.

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Section: Verificationmentioning

confidence: 99%