2017
DOI: 10.1109/jssc.2017.2669025
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Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

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Cited by 23 publications
(11 citation statements)
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“…The measurement speed could also be improved significantly by configuring the CCO as a TDC and measuring the Fd phase instead of frequency [5]. Utilizing phase measurements could enable a complete measurement in one or two GHz-level frequency cycles.…”
Section: Measured Silicon Resultsmentioning
confidence: 99%
See 3 more Smart Citations
“…The measurement speed could also be improved significantly by configuring the CCO as a TDC and measuring the Fd phase instead of frequency [5]. Utilizing phase measurements could enable a complete measurement in one or two GHz-level frequency cycles.…”
Section: Measured Silicon Resultsmentioning
confidence: 99%
“…However, this GB costs significant additional power, since power increases as Vdd 2 and therefore also increases as GB 2 . To optimize the power consumption, there have been significant efforts to detect and mitigate these droops, to reduce the GB [2][3][4][5][6][7][8][9][10][11][12].…”
Section: Introductionmentioning
confidence: 99%
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“…In the same context, several studies either in the hardware or in the software level have been presented to mitigate the effects of voltage noise [5] [84] [149] [191] [192] [193] [194] [195] [196] or to recover from them after their occurrence [197]. Some works [198], [199], [200], and [201] focus on the development of electrical simulation framework for power-delivery analysis Reddi et al [5] show that different workloads have different voltage margins and different voltage droop activity based on a 2-core microprocessor.…”
Section: Related Workmentioning
confidence: 99%