Power Gating Method for Power Supply Noise Suppression

Abstract

As technology scaling down, power consumption of integrated circuits increases tremendously due to leakage current. Power gating is one of the most effective techniques to reduce leakage power by shutting off idle blocks from power supply. However, during a power-mode transition, an instantaneous charge current passes through the switch transistor, and creates current surge elsewhere. Because of the self-inductance of the off-chip bonding wires and parasitic inductance inherent to the on-chip power rails, these surges result in severe simultaneous switching noise (SSN), which results in function failure.Based on typical power delivery network, it is found that the magnitude of SSN would accumulate positively with Fcurrent = 1/(n + 1) Resonant, and the magnitude of SSN would accumulate negatively with Fcurrent = 1/(n + 1/2) Resonant. In this paper, a new method is proposed to suppress the power supply noise based on its periodic characteristic. By cutting power grid, partition of switch transistors and controlling their switching, smaller segmented charge current magnitude and controllable period can be provided into gated block for mitigating noise. The power supply noise produced by charge current can be suppressed through adjusting the delay of charge current and the magnitude of charge current which is verified by simulation. Compared to conventional power gating structures, this method can save decap area and is practical and flexible to embed in an optimization flow. A principle for controllable switch transistor chain is also given to simplify the high speed power delivery network design.