Power estimations vs. power measurements in Spartan-6 devices

Oliver, Juan Pablo; Acle, Julio Pérez; Boemo, Eduardo

doi:10.1109/spl.2014.7002214

Cited by 8 publications

(6 citation statements)

References 11 publications

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“…While deriving the DPCEM, DPC values of the FPGA for all the design variants are required in order to gather the initial data for model derivation. Software prediction tools like Xilinx Power Analyzer can be used for this purpose if accurate switching activity factors are available [64][65][66]. We have used the method of actual DPC measurement to maximize the accuracy of the model derivation process.…”

Section: Power Consumption Measurement Methodsmentioning

confidence: 99%

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Sharma

Kirischian

Kirischian³

2018

Computers

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Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

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Section: Power Consumption Measurement Methodsmentioning

confidence: 99%

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Sharma

Kirischian

Kirischian³

2018

Computers

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“…The work presented in Landsiedel et al 14 predicts the energy consumption of a whole sensor network based on the electric current measurement of a single sensor node. The authors in earlier works 9,8,15,16 measured current using a multimeter to find the consumed power of a CPU. In Kulkarni and Udupi, 17 a method for energy estimation at the instruction level for ARM Cortex M4 processor was presented.…”

Section: Measurement-based Methodsmentioning

confidence: 99%

A practical microwatt-meter for electrical energy measurement in programmable devices

Al-Shorman

Al-Kofahi

2018

Measurement and Control

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Background: In this work, an accurate low-cost power microwatt-meter is designed, built, and tested. This microwatt-meter is found to be capable of measuring power consumption in a wide range of devices and sensors, such as nodes in wireless sensor networks, microcontrollers in Internet of Things devices, and Field Programmable Gate Arrays. Methods: The paper examines the usage of the microwatt-meter for the measurement of power consumption in digital devices as they execute program instructions, ranging from a low-level single step (instruction) in an assembly program to a high-level sophisticated program or system. Results: The results obtained showed that the microwatt-meter is highly accurate. It can measure the energy consumed by any of the devices/programs/instructions in a digital system with accuracy levels ranging between 0.5% and 2.5% (depending on the application). Conclusion: The accuracy of the microwatt-meter is validated using the fundamental conservation of energy law and a comparison with multimeter current measurements is presented.

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“…Several research papers have reported the direct on-board power measurements and compared them to estimates through power estimation tools. For example, [25] and [26] reported experimental measurements of power consumption for a core logic of 45-nm Spartan 6 field programmable gate array (FPGA) and core logic of a 65-nm Cyclone III FPGA, respectively, and compared them to values predicted by a power estimation tool. In [25], different types of 32 × 32 bit multipliers were implemented using both look-up tables (LUTs) and embedded units, as case studies.…”

Section: B Related Workmentioning

confidence: 99%

“…For example, [25] and [26] reported experimental measurements of power consumption for a core logic of 45-nm Spartan 6 field programmable gate array (FPGA) and core logic of a 65-nm Cyclone III FPGA, respectively, and compared them to values predicted by a power estimation tool. In [25], different types of 32 × 32 bit multipliers were implemented using both look-up tables (LUTs) and embedded units, as case studies. Their findings show a high difference between the measured and estimated power values, especially in circuits with longer combinatorial paths, where the tools tend to over estimate the number of produced glitches.…”

Section: B Related Workmentioning

confidence: 99%

Computational Power Evaluation for Energy-Constrained Wireless Communications Systems

Tariq

Al-Dweik

Mohammad

et al. 2020

IEEE Open J. Commun. Soc.

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Estimating the power consumption and computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems is critical to assess the feasibility of implementing such algorithms in hardware, and for designing energy-constrained communications systems. Therefore, this paper presents a novel approach, based on practical system measurements using field programmable gate array (FPGA) and application-specific integrated circuit (ASIC), to evaluate the power consumption and the associated computational complexity of the most common mathematical operations performed within various DSP algorithms. Using the proposed approach, a new metric is developed for mapping the computational complexity to the computational power consumed by the mathematical operation in wireless transceivers. This allows combining the commonly used computational complexity metrics that are typically computed for each mathematical operation separately. Consequently, a single unified metric can be used to describe the entire algorithm. Therefore, the comparison and trade-offs between different algorithms become easier and more informative. The developed approach is used to evaluate the computational power of several DSP algorithms used in wireless communications systems, and perform thorough computational complexity comparisons. The obtained results reveal that computational complexity comparisons using different mathematical operations can be highly misleading in several scenarios. The power consumption evaluation of the considered DSP algorithms show that some algorithms may require a prohibitively high power, which makes such algorithms unsuitable for powerconstrained wireless communications systems. The results also show that the proposed methodology can be adopted for various hardware implementation, however, some calibration might be required based on the adopted platform.

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Power estimations vs. power measurements in Spartan-6 devices

Cited by 8 publications

References 11 publications

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

A practical microwatt-meter for electrical energy measurement in programmable devices

Computational Power Evaluation for Energy-Constrained Wireless Communications Systems

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