Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet

El-Maksoud, Ahmed J. Abd; Ebbed, Mohamed; Khalil, A. H.; Mostafa, Hassan

doi:10.1109/access.2021.3126838

Cited by 14 publications

(3 citation statements)

References 30 publications

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“…It seems impossible to make the real-time inference of CNN-based object detection on mobile FPGA devices which have limited hardware resources such as memory size and lower processor performance. In these power and hardware resource-limited circumstances, to improve performance and reduce power consumption, many researchers have proposed CNN accelerators at various design levels including system level, application level, architecture level, and transistor level [7], [8], [9]. Recent studies have proposed a flexible CNN accelerator design for FPGA implementation at the system level and a flexible FPGA accelerator for various CNN architectures from lightweight CNN to large-scale CNN [11], [12], [13], [14], [15], [16].…”

Section: Convolutional Neural Network(cnn)-based Object Detection App...mentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.INDEX TERMS FPGA accelerator, CNN accelerator, RT level design techniques, low power techniques, reconfigurable accelerator, CNN-based object detection, low power consumption, high performance, mobile FPGA.

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Section: Convolutional Neural Network(cnn)-based Object Detection App...mentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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“…The proposed architecture is implemented on the Xilinx Virtex-7 FPGA platform and achieves the performance of 1.34 GOP/s. Ahmed et al [81] proposed an FPGA-based Low Power CNN (LP-CNN) accelerator based on GoogLeNet CNN. The proposed accelerator uses quantization and weight pruning techniques to reduce memory size.…”

Section: B Accelerators For a Specific Algorithmmentioning

confidence: 99%

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

et al. 2022

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In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.INDEX TERMS Machine learning, field programmable gate array (FPGA), deep neural networks (DNN), deep learning (DL), application specific integrated circuits (ASIC), artificial intelligence (AI), central processing unit (CPU), graphics processing unit (GPU), hardware accelerators. FIGURE 3. A single ANN neuron with its elements (inputs, weights, bias, summer, activation function, and output).

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“…They significantly reduce the hardware requirements with a minimal impact on the accuracy [8,9]. An interesting, practical use of FPGA systems to implement CNN is presented in the works [10][11][12][13]. Several algorithmic optimization strategies used in FPGA hardware for CNNs are discussed, and a few of neural network FPGA-based accelerators architectures are presented.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Field-Programmable Gate Array Rapid Implementation of a Structural Health Monitoring System

Rosół,

Kula

2024

Energies

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System health monitoring (SHM) of a ball screw laboratory system using an embedded real-time platform based on Field-Programmable Gate Array (FPGA) technology was developed. The ball screw condition assessment algorithms based on machine learning approaches implemented on multiple platforms were compared and evaluated. Studies on electric power consumption during the processing of the proposed structure of a neural network, implementing SHM, were carried out for three hardware platforms: computer, Raspberry Pi 4B, and Kria KV260. It was found that the average electrical power consumed during calculations is the lowest for the Kria platform using the FPGA system. However, the best ratio of the average power consumption to the accuracy of the neural network was obtained for the Raspberry Pi 4B. The concept of an efficient and energy-saving hardware platform that enables monitoring and analysis of the operation of the selected dynamic system was proposed. It allows for easy integration of many software environments (e.g., MATLAB and Python) with the System-on-a-Chip (SoC) platform containing an FPGA and a CPU.

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Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet

Cited by 14 publications

References 30 publications

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

An Energy-Efficient Field-Programmable Gate Array Rapid Implementation of a Structural Health Monitoring System

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