Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator

Penny, Wagner; Ucker, Mariana; Machado, Italo; Agostini, Luciano; Palomino, Daniel; Porto, Marcelo

doi:10.1109/icecs.2018.8618009

Cited by 6 publications

(13 citation statements)

References 12 publications

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“…In Table VII, we can see that our solution consumes more power and area resources compared to the implementation of the approximate hardware in HEVC [15] and the precise hardware in VVC [10]. We also computed the energy/pixel consumption, which represents how much energy is spent in a second to process each input pixel.…”

Section: Resultsmentioning

confidence: 99%

“…Approximate architectures were also proposed to further extend the area and power savings of dedicated HEVC interpolation filter hardware. Penny et al [15] propose a configurable hardware that supports the 8-tap HEVC interpolation filters and 6-tap approximate interpolation filters by removing the leftmost and rightmost taps of the original filter. The approach increases BD-Rate in 0.527% compared to the original HEVC interpolation filters.…”

Section: Filters Coefficientsmentioning

confidence: 99%

“…All those works [11][12][13][14][15][16]18] target HEVC interpolation filtering, which is 17× less complex than VVC interpolation filtering, as we motivated in the introduction. Performance, power, and energy of HEVC and VVC interpolation filters cannot be directly compared.…”

Section: Filters Coefficientsmentioning

confidence: 99%

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Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Silva

Siqueira

Grellert

et al. 2021

JICS

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The new Versatile Video Coding (VVC) standard was recently developed to improve compression efficiency of previous video coding standards and to support new applications. This was achieved at the cost of an increase in the computational complexity of the encoder algorithms, which leads to the need to develop hardware accelerators and to apply approximate computing techniques to achieve the performance and power dissipation required for systems that encode video. This work proposes the implementation of an approximate hardware architecture for interpolation filters defined in the VVC standard targeting real-time processing of high resolution videos. The architecture is able to process up to 2560x1600 pixels videos at 30 fps with power dissipation of 23.9 mW when operating at a frequency of 522 MHz, with an average compression efficiency degradation of only 0.41% compared to default VVC video encoder software configuration.

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Section: Resultsmentioning

confidence: 99%

Section: Filters Coefficientsmentioning

confidence: 99%

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Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Silva

Siqueira

Grellert

et al. 2021

JICS

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“…Most video coding tools are intrinsically resilient to some imprecision level, especially at the prediction steps. In the case of inter-frame prediction (where the FME is included), each block of the current frame is compared with other blocks in previously processed frames, in order to define which one is the most similar to the current one [9]. This way, if a near-optimal block is selected, the encoding and decoding will work correctly, but with some losses in coding efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…Multiple related works propose hardware architectures employing approximate computing for video coding, like [9] [13] [14], but those works are focused in the HEVC standard [15]. On the other hand, some works in the literature target hardware designs for the AV1 interpolation filters.…”

Section: Introductionmentioning

confidence: 99%

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

Domanski

Kolodziejski²,

Corrêa

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Modern video encoders like the AOM Video 1 (AV1) implement several complex tools to allow the required high level of compression efficiency. The Fractional Motion Estimation (FME) is one of these tools and in AV1 the FME defines 90 different filters. To handle such complexity, hardware acceleration using approximate computing has become an alternative to be explored. This paper presents an approximate solution for the AV1 FME interpolation filters based on the approximation of the original filter coefficients intending to generate more hardware friendly coefficients. The approximated version was designed in hardware and can achieve real-time interpolation for UHD 8K videos at 30 frames per second, when synthesized using 40nm TSMC standard-cells technology. The designed architecture dissipates 26.79mW which represents more than 80% power reduction when compared to the original precise solution. The approximation implied in a small average coding efficiency degradation of 0.54% in BD-BR. When comparing with related works, this architecture reaches an expressive power reduction (2.1 to 4.8 times) even supporting more complex tools.

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High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec

Freitas

Diniz

Grellert

et al. 2021

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

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Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator

Cited by 6 publications

References 12 publications

Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec

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