Power-efficient and highly scalable parallel graph sampling using FPGAs

Tariq, Usman; Cheema, Umer I.; Saeed, Fahad

doi:10.1109/reconfig.2017.8279806

Cited by 6 publications

(4 citation statements)

References 16 publications

(15 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…GraphSAINT [11], [12] explores three graph sampling methods, i.e., random vertex and edge sampling, and random walk based sampler, but fails to arrive at a universal framework. [76] supports deletion based sampling algorithms [77]. But this design is inefficient for large graphs that need to remove most edges.…”

Section: Related Workmentioning

confidence: 99%

C-SAW: A Framework for Graph Sampling and Random Walk on GPUs

Pandey,

Li,

Hoisie

et al. 2020

Preprint

View full text Add to dashboard Cite

Many applications require to learn, mine, analyze and visualize large-scale graphs. These graphs are often too large to be addressed efficiently using conventional graph processing technologies. Fortunately, recent research efforts find out graph sampling and random walk, which significantly reduce the size of original graphs, can benefit the tasks of learning, mining, analyzing and visualizing large graphs by capturing the desirable graph properties. This paper introduces C-SAW, the first framework that accelerates Sampling and Random Walk framework on GPUs. Particularly, C-SAW makes three contributions: First, our framework provides a generic API which allows users to implement a wide range of sampling and random walk algorithms with ease. Second, offloading this framework on GPU, we introduce warp-centric parallel selection, and two novel optimizations for collision migration. Third, towards supporting graphs that exceed the GPU memory capacity, we introduce efficient data transfer optimizations for out-of-memory and multi-GPU sampling, such as workload-aware scheduling and batched multi-instance sampling. Taken together, our framework constantly outperforms the state of the art projects in addition to the capability of supporting a wide range of sampling and random walk algorithms.

show abstract

Section: Related Workmentioning

confidence: 99%

C-SAW: A Framework for Graph Sampling and Random Walk on GPUs

Pandey,

Li,

Hoisie

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…The targeted graphs for this sampling method are gene correlation networks where we have to maintain highly connected parts of the graph since they indicate important functional units of the gene product. FPGA Techniques: In our previous publication [29], we implemented a strategy to do parallel sampling for a static graph using OpenCL for FPGAs. Though energy efficient, this strategy only works for a single graph in memory and does not consider the time to read the graph from the storage device, which can be considerable depending on the graph size.…”

Section: A Literature Reviewmentioning

confidence: 99%

Parallel Sampling-Pipeline for Indefinite Stream of Heterogeneous Graphs using OpenCL for FPGAs

Tariq

Saeed

2018

2018 IEEE International Conference on Big Data (Big Data)

Self Cite

View full text Add to dashboard Cite

In the field of data science, a huge amount of data, generally represented as graphs, needs to be processed and analyzed. It is of utmost importance that this data be processed swiftly and efficiently to save time and energy. The volume and velocity of data, along with irregular access patterns in graph data structures, pose challenges in terms of analysis and processing. Further, a big chunk of time and energy is spent on analyzing these graphs on large compute clusters and/or data-centers. Filtering and refining of data using graph sampling techniques are one of the most effective ways to speed up the analysis. Efficient accelerators, such as FPGAs, have proven to significantly lower the energy cost of running an algorithm. To this end, we present the design and implementation of a parallel graph sampling technique, for a large number of input graphs streaming into a FPGA. A parallel approach using OpenCL for FPGAs was adopted to come up with a solution that is both time-and energyefficient. We introduce a novel graph data structure, suitable for streaming graphs on FPGAs, that allows time-and memory-efficient representation of graphs. Our experiments show that our proposed technique is 3x faster and 2x more energy efficient as compared to serial CPU version of the algorithm.

show abstract

“…Multicore and manycore devices such as GPUs, Intel-Phi and FPGAs have been shown to be useful for scaling big data problems for variety of applications [26] [9]. With the advent of these devices, there is a need to develop well-designed and scalable algorithms that can exploit the underlying HPC architecture [15] [18].…”

Section: Introductionmentioning

confidence: 99%

“…However, despite its advantages, it is a very tedious task to develop an optimized GPU algorithm. Because of the application specific designs of GPU algorithms, re-using existing designs with minor tweaks is not possible and naively designed algorithms may perform even poorer than their sequential versions [26]. To facilitate rapid designing of an optimized GPU algorithm, a set of fundamental guidelines and generic principles needs to be available.…”

Section: Introductionmentioning

confidence: 99%

GPU-DAEMON: GPU algorithm design, data management & optimization template for array based big omics data

Awan

Eslami

Saeed

2018

Computers in Biology and Medicine

Self Cite

View full text Add to dashboard Cite

In the age of ever increasing data, faster and more efficient data processing algorithms are needed. Graphics Processing Units (GPU) are emerging as a cost-effective alternative architecture for high-end computing. The optimal design of GPU algorithms is a challenging task which requires thorough understanding of the high performance computing architecture as well as the algorithmic design. The steep learning curve needed for effective GPU-centric algorithm design and implementation requires considerable expertise, time, and resources. In this paper, we present GPU-DAEMON, a GPU Data Management, Algorithm Design and Optimization technique suitable for processing array based big omics data. Our proposed GPU algorithm design template outlines and provides generic methods to tackle critical bottlenecks which can be followed to implement high performance, scalable GPU algorithms for given big data problem. We study the capability of GPU-DAEMON by reviewing the implementation of GPU-DAEMON based algorithms for three different big data problems. Speed up of as large as 386x (over the sequential version) and 50x (over naive GPU design methods) are observed using the proposed GPU-DAEMON. GPU-DAEMON template is available at https://github.com/pcdslab/GPU-DAEMON and the source codes for GPU-ArraySort, G-MSR and GPU-PCC are available at https://github.com/pcdslab.

show abstract

Power-efficient and highly scalable parallel graph sampling using FPGAs

Cited by 6 publications

References 16 publications

C-SAW: A Framework for Graph Sampling and Random Walk on GPUs

C-SAW: A Framework for Graph Sampling and Random Walk on GPUs

Parallel Sampling-Pipeline for Indefinite Stream of Heterogeneous Graphs using OpenCL for FPGAs

GPU-DAEMON: GPU algorithm design, data management & optimization template for array based big omics data

Contact Info

Product

Resources

About