Power Distribution Networks with On-Chip Decoupling Capacitors

Popovich, Mikhail; Mezhiba, Andrey V.; Friedman, Eby G.

doi:10.1007/978-0-387-71601-5

Cited by 113 publications

(94 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1 care is needed. In this direction, the so-called flip-chips, with an array bonding power distribution network, represented a substantial improvement, and are actually becoming more and more used by chip designers ( [15], [14]). …”

Section: Introduction and Main Resultsmentioning

confidence: 99%

See 1 more Smart Citation

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

Aguareles

Haro²,

Rius³

et al. 2011

Eur. J. Appl. Math

View full text Add to dashboard Cite

Abstract. We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits.In this model the voltage is the solution of a Poisson equation in an infinite planar domain whose boundary is an array of circular pads of radius ε, and we deal with the singular limit ε → 0 case. In comparison with approximations that appear in the electronic engineering literature, our formula is more complete since we have obtained terms up to order ε 15 . A procedure will be presented to compute all the successive terms, which can be interpreted as using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and of the Gauss constant G.

show abstract

Section: Introduction and Main Resultsmentioning

confidence: 99%

“…This bounce, which produces a reduction in the supply voltage (known as Power Supply Noise, PSN) decreases the gate drive strength, thus lowering the circuit speed performance [14]. A good PDN design must reduce the PSN below a specified value.…”

Section: The Modelmentioning

confidence: 99%

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

Aguareles

Haro²,

Rius³

et al. 2011

Eur. J. Appl. Math

View full text Add to dashboard Cite

show abstract

“…In modern system-on-chip design, supply-voltage-noise induced reliability issues are becoming increasingly challenging due to increasing current density [1]. Among the various sources of voltage noise, IR drop refers to the resistive drop across metal wires in the power delivery network (PDN).…”

Section: Introductionmentioning

confidence: 99%

Walking pads: Fast power-supply pad-placement optimization

Meyer

Zhang

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

View full text Add to dashboard Cite

Abstract-We propose a novel C4 pad placement optimization framework for 2D power delivery grids: Walking Pads (WP). WP optimizes pad locations by moving pads according to the "virtual forces" exerted on them by other pads and current sources in the system. WP algorithms achieve the same IR drop as state-of-theart techniques, but are up to 634X faster. We further propose an analytical model relating pad count and IR drop for determining the optimal pad count for a given IR drop budget.

show abstract

“…Different P/G structures have been compared in [7,8], where an interdigitated structure is shown to achieve the greatest reduction in inductance.…”

Section: Introductionmentioning

confidence: 99%

Line width optimization for interdigitated power/ground networks

Jakushokas

Friedman

2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

Self Cite

View full text Add to dashboard Cite

Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with an interdigitated structure. A closed-form solution for determining the optimal power and ground wire width is described, producing the minimum impedance within an interdigitated structure. The optimal wire width is determined under different physical network dimensions and signal frequencies, suggesting useful trends for interdigitated power and ground networks. In addition, a closed-form expression for the optimal wire width is determined that minimizes the voltage drop over a single metal layer of an interdigitated power/ground network.

show abstract

Power Distribution Networks with On-Chip Decoupling Capacitors

Cited by 113 publications

References 0 publications

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

Walking pads: Fast power-supply pad-placement optimization

Line width optimization for interdigitated power/ground networks

Contact Info

Product

Resources

About