Power consumption reduction in CPU datapath using a novel clocking scheme

Megalingam, Rajesh Kannan; Hassan, Taha; Vivek, P.; Mohan, Ashwin; Rao, M. Tanmay

doi:10.1109/iccsit.2009.5234658

Cited by 5 publications

(2 citation statements)

References 4 publications

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“…Other works that utilize DVFS include Chen et al [2012a] and Kim et al [2012], whereas Kahng et al [2013] propose some improvements over DVFS itself. Going even deeper into power limitation, Megalingam et al [2009] propose a novel clocking scheme on a pipelined RISC CPU that is able to reduce power consumption by 50%. Unlike DVFS approaches or ones using clock gating, vCAP [Hankendi et al 2013] uses co-scheduling for resource allocation in order to maximize the performance under power and performance constraints.…”

Section: Dvfs and Alternativesmentioning

confidence: 99%

Cloud Computing

Mastelić

Oleksiak

Claußen³

et al. 2014

ACM Comput. Surv.

227

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Cloud computing is today's most emphasized Information and Communications Technology (ICT) paradigm that is directly or indirectly used by almost every online user. However, such great significance comes with the support of a great infrastructure that includes large data centers comprising thousands of server units and other supporting equipment. Their share in power consumption generates between 1.1% and 1.5% of the total electricity use worldwide and is projected to rise even more. Such alarming numbers demand rethinking the energy efficiency of such infrastructures. However, before making any changes to infrastructure, an analysis of the current status is required. In this article, we perform a comprehensive analysis of an infrastructure supporting the cloud computing paradigm with regards to energy efficiency. First, we define a systematic approach for analyzing the energy efficiency of most important data center domains, including server and network equipment, as well as cloud management systems and appliances consisting of a software utilized by end users. Second, we utilize this approach for analyzing available scientific and industrial literature on state-of-the-art practices in data centers and their equipment. Finally, we extract existing challenges and highlight future research directions.

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Section: Dvfs and Alternativesmentioning

confidence: 99%

Cloud Computing

Mastelić

Oleksiak

Claußen³

et al. 2014

ACM Comput. Surv.

227

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“…Previous researches have presented a various approaches for optimizing power consumption, such as clock gating [1,2], buffer insertion [3,4], multi-supply voltage (MSV) designs [5], Globally Asynchronous Locally Synchronous (GALS) [6], and parallelism and pipeline [7]. Among these approaches, clock gating technique has been used widely in high performance VLSI design to reduce clock network power consumption.…”

Section: Introductionmentioning

confidence: 99%

Clock tree construction using gated clock cloning

Chen

Chang

Hung

et al. 2012

2012 4th Asia Symposium on Quality Electronic Design (ASQED)

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Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter γ that may be used to adjust the tradeoff between clock gating cell and buffer. The experimental results show that the number of clock gating cells and buffers reduced in each phase in our algorithm. Our solutions are better than greedy approach.

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Implementation of power estimation methodology for intellectual property at SoC level

Chalil

2017

2017 2nd International Conference on Communication and Electronics Systems (ICCES)

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Power consumption reduction in CPU datapath using a novel clocking scheme

Cited by 5 publications

References 4 publications

Cloud Computing

Cloud Computing

Clock tree construction using gated clock cloning

Implementation of power estimation methodology for intellectual property at SoC level

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