Power Consumption Estimations vs Measurements for FPGA-Based Security Cores

Meintanis, D.; Papaefstathiou, Ioannis

doi:10.1109/reconfig.2008.45

Cited by 20 publications

(9 citation statements)

References 2 publications

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“…As those numbers clearly demonstrate our FPGA-based system is more than 30 times faster than an Atom while its energy consumption is more than 90% lower. However, this comparison may not be extremely fair since for the Virtex-II we have actually measured the energy consumption while for the Atom we have estimated it using a certain tool; this may be slightly misleading since as it is demonstrated in [2] the power estimation are quite pessimistic (i.e. the reported energy consumption is higher than the actual one).…”

Section: Performance Resultsmentioning

confidence: 99%

“…Reconfigurable hardware is considered more power hungry than low-power microcontrollers and therefore it has not been widely considered for WSN applications. However FPGAs allow for significantly higher performance and energy-efficient processing when implementing certain demanding networking tasks [2], [3]. Furthermore, since their functionality can be reprogrammed either prior to deployment or while in use, they are very promising candidates for general-purpose nodes.…”

Section: Introductionmentioning

confidence: 99%

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Fast and power-efficient hardware implementation of a routing scheme for WSNs

Mplemenos

Papaefstathiou

2012

2012 IEEE Wireless Communications and Networking Conference (WCNC)

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One of the most rapidly expanding areas, nowadays, in networking systems is the Wireless Sensor Network (WSN). Typically WSNs rely on multi-hop routing protocols which must be able to establish communication among nodes and guarantee packet deliveries. In this paper, we present a novel approach for the implementation of the WSN routing protocols, which takes advantage of modern FPGAs in order to provide faster routing decisions while consuming significantly less energy than existing systems. Despite our focus on a particular routing protocol (GPSR), the platform developed has the additional advantage that due to the reconfigurability feature of the FPGA it can efficiently execute different routing protocols based on the requirements of the different WSN applications. As our real world experiments demonstrate, we accelerated the execution of the most widely used WSN routing protocol (GPSR) by at least 31 times when compared to the speed achieved when the exact same protocol is executed on a low power Intel Atom processor. More importantly by utilizing a high-end FPGA the overall energy consumption was reduced by more than 90%.

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Section: Performance Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fast and power-efficient hardware implementation of a routing scheme for WSNs

Mplemenos

Papaefstathiou

2012

2012 IEEE Wireless Communications and Networking Conference (WCNC)

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“…While deriving the DPCEM, DPC values of the FPGA for all the design variants are required in order to gather the initial data for model derivation. Software prediction tools like Xilinx Power Analyzer can be used for this purpose if accurate switching activity factors are available [64][65][66]. We have used the method of actual DPC measurement to maximize the accuracy of the model derivation process.…”

Section: Power Consumption Measurement Methodsmentioning

confidence: 99%

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Sharma

Kirischian

Kirischian³

2018

Computers

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Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

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“…The paper in [11] presents several differences between measured and estimated power consumption, which varied from 15.52% to 208% for the Xilinx devices (Virtex II-Pro, and Spartan 3), and from 5.64% to 32.15% for the Altera device (Cyclone II).…”

Section: Related Workmentioning

confidence: 99%

Power estimations vs. power measurements in Cyclone III devices

Oliver

Boemo

2011

2011 VII Southern Conference on Programmable Logic (SPL)

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This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.

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Power Consumption Estimations vs Measurements for FPGA-Based Security Cores

Cited by 20 publications

References 2 publications

Fast and power-efficient hardware implementation of a routing scheme for WSNs

Fast and power-efficient hardware implementation of a routing scheme for WSNs

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Power estimations vs. power measurements in Cyclone III devices

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