Power-aware test generation with guaranteed launch safety for at-speed scan testing

Abstract

At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.

Thermal Issues in Testing of Advanced Systems on Chip

“…At-speed scan-based testing may be affected by launch safety issues [Wen11]. This means that the test results are incorrect because of excessive launch switching activity which is related to the test stimulus launch in the at-speed test cycle.…”

“…This means that the test results are incorrect because of excessive launch switching activity which is related to the test stimulus launch in the at-speed test cycle. A power-aware test generation flow is proposed in [Wen11] to guarantee a safe launch. The proposed rescue and mask scheme targets the excessive switching activity around the long path that the test vector targets.…”

“…If the new power value is still too large the test responses are masked. The proposed approach guarantees launch safety with a negligible impact on test quality and costs [Wen11].…”

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

“…• Toward Capture Power Safety A typical capture-power-safe solution for stored pattern testing is rescue-&-masking [11], [12], in which (1) the local switching activity around each long sensitized path (LSP) of a test vector is checked to determine if it is a risky path (i.e., an LSP whose surrounding switching activity is so high that the test response from the LSP is possibly-erroneous as an uncertain value); (2) for any risky path, X-filling [17] is conducted in a pinpoint manner to directly reduce its surrounding switching activity; (3) if the effect of switching activity reduction is insufficient to turn a risky path into a non-risky path, the uncertain test response from the risky path will be masked to instruct the tester not to use it. This way, any adverse impact of excessive capture power on final test results is avoided, thus realizing capture power safety.…”

“…These paths are risky paths (e.g., P in Fig. 2) since test responses from them are possibly-erroneous (i.e., test response values become uncertain) [11], [12]. At T 2 (also shown in Fig.…”