Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

Ning, Ke; Kaeli, David

doi:10.1007/11587514_7

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…The workload and memory sizes will affect the results of page remapping algorithms. We produced profiles of external memory bus activity using the timing/power model developed in our previous research [12]. The model allows us to simulate many processor-to-memory configurations accurately, and has been calibrated against actual hardware.…”

Section: Methodsmentioning

confidence: 99%

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External memory page remapping for embedded multimedia systems

NingKe

KaeliDavid

2007

SIGPLAN Not.

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As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded systems. Both hardware and software approaches can be explored to balance the power/performance tradeoff associated with the external memory.In this paper we present a hardware-based, programmable external memory page remapping mechanism which can significantly improve performance and decrease the power budget due to external memory bus accesses. Our approach was developed by studying common data access patterns present in embedded multimedia applications. In the paper, we evaluate a mechanism that can perform page remapping of external memory. We also develop an efficient algorithm to map application data and instruction memory into external memory pages. We employ graph-coloring techniques to guide the page mapping procedure. The objective is to avoid page misses by remapping conflicting pages to different memory banks (i.e., by assigning them different colors). Our algorithm can significantly reduce the memory page miss rate by 70-80% on average. For a 4-bank SDRAM memory system, we reduced external memory access time by 12.6% . The proposed algorithm can reduce power consumption in majority of the benchmarks, averaged by 13.2% of power reduction. Combining the effects of both power and delay, our algorithm can benefit significantly to the total energy cost.

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Section: Methodsmentioning

confidence: 99%

“…The more banks in a memory system, the more improvement our page remapping algorithm can produce. External bus power can be reduced if the signal toggling rate on the external bus decreases [12]. Figure 11 shows a mixture of results in terms of power savings.…”

Section: Power and Delaymentioning

confidence: 99%

External memory page remapping for embedded multimedia systems

NingKe

KaeliDavid

2007

SIGPLAN Not.

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“…With N reference frames and additional read and write to the external memory for the current frame, a total of (11.12N+2.78) Gbps are read and around 2.78 Gbps written. Note that the external bus power dissipation is directly proportional to the total number of bit-toggles per transition [44]. This enormous amount of data results in high latency and energy consumption (around 40% of the total system energy is consumed by the external IO [43] [22]).…”

Section: Fig 4 Block Matching Memory Access Comparison Between Hevc mentioning

confidence: 99%

AMBER: Adaptive energy management for on-chip hybrid video memories

Khan

Shafique

Henkel

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The ever increasing leakage power of memories in a system has motivated researches for exploiting unconventional memory architectures. Non-Volatile Memory (NVM) used in conjunction with the conventional on-chip SRAMs has given birth to the hybrid memory paradigm, which can be intelligently exploited to reduce the energy consumption while tackling the high read and write latencies of NVMs. We present a novel scheme AMBER that aims at minimizing the total memory energy consumption of a video processing system by leveraging the application-specific properties and distinct latency and power properties of different memory types. AMBER also features architectural support for data-fetching from external memory and adaptively filling the different on-chip memories. We employ AMBER in the next-generation High Efficiency Video Coding (HEVC) standard to minimize the energy consumption of the new complex motion prediction process. Experimental results demonstrate that our AMBER scheme achieves significant energy savings (average 43%) for the on-chip memory.

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