Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers

Paim, Guilherme; Rocha, Leandro M. G.; Santana, Gustavo M.; Soares, Laura; Costa, Eduardo; Bampi, Sérgio

doi:10.1109/tcsi.2018.2868513

Cited by 22 publications

(4 citation statements)

References 31 publications

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“…Finally, the synthesis tool runs again but using as input the previously generated netlist and the stimuli file for the power estimation. Therefore, we use a methodology for precise power dissipation extraction with the following steps [19]. First, all designs are synthesized with the Cadence Genus Synthesis [20] tool with the Physically-Aware Layout Estimation (PLE) mode, which includes an estimation of the wire length and the effects of these wires in terms of area, power dissipation and critical path.…”

Section: A Power Extraction Methodologymentioning

confidence: 99%

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Rocha

Paim

Santana

et al. 2020

JICS

Self Cite

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Arithmetic modules usually have a significant impact on performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). Exploring implementation trade-offs in these circuits is of utmost importance in low-power and low-cost devices such as sensors in IoT devices which often have stringent requirements. Multipliers are of particular concern due to their ubiquitous use in DSP algorithms and their inherent implementation complexity. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Several partial product encoders were combined with multiple compression trees to generate multipliers that were synthesized in a commercial 65 nm to obtain area, power, and timing results.

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Section: A Power Extraction Methodologymentioning

confidence: 99%

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Rocha

Paim

Santana

et al. 2020

JICS

Self Cite

View full text Add to dashboard Cite

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“…e proposed architecture maximally reused the hardware resources by rearranging the order of input data for different transform sizes while still exploiting the butterfly property. In [9], a new approximation for the 8-point discrete tchebichef transform was proposed with a higher power-and compression efficiency by exploring coefficient truncation. In [10], an image-dependent optimum nonnegative integer bit allocation algorithm was proposed, which was then mapped into desired image-independent solution via utilization of a prepared combined image and proposed modified step size mapping technique.…”

Section: Related Workmentioning

confidence: 99%

Improving the Quality of Left-Behind Children’s Participation in Sports through Wireless Network Monitoring

Zhao

2021

Mobile Information Systems

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Urbanization is the process that people shift from rural to urban areas, which has led to large numbers of left-behind children in China. The left-behind children stay in rural regions of China while their parents work in urban areas. The left-behind children have few opportunities to participate in sports due to the lacking of concern, and it is not of high quality even though they participate in sports. Therefore, it is necessary to improve the quality of left-behind children's sports participation through wireless network monitoring. Wireless network monitoring transmits high-definition (HD) video streaming in real time to facilitate feedback timely. This paper studies the two-dimensional (2D) integer discrete cosine transform (DCT) and analyzes the reason for image distortion, then an improved DCT coefficient quantization approach is proposed for long-distance real-time transmission of HD video streaming, and a noise processing with a zero-mean noise processing is added in optimized approach to solve the image distortion problem. The experimental results show that the proposed improved approach has a good performance in reducing the blocking artifacts, and within the image reconstruction, the proposed approach improves the subjective video quality.

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“…Another clear example of data approximation, acting on both data precision and amount, is the work proposed by Paim et. al [41] on approximating the transformation step, that is typical of video coding applications. Transform operations are pervasive in video coding algorithms.…”

Section: Data Level Approximationmentioning

confidence: 99%

“…Paim et. al [41], on the top of an already approximated (computational level approximation that will be discussed later on) version of the DTT matrix [40], apply truncation and pruning in order to simplify the computation and the system (an hardware accelerator) itself, resulting in area, power and compression efficiency improvements. Firstly, a quality-driven quantization of the DTT matrix coefficients, that is a common process in computational level approximation of transform matrices, has been performed.…”

Section: Data Level Approximationmentioning

confidence: 99%

Reconfigurable and approximate computing for video coding

Palumbo

2019

VLSI Architectures for Future Video Coding

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Systems perception capabilities are fundamental to make modern interconnected systems smart and, in this context, video coding is certainly a key technology. Video coding standards have been traditionally based on monolithic specifications coupled to a fixed set of profiles, capable of implementing different sub-set of functionalities of the given reference standard. Standards and profiles typically offer different features and enable different trade-offs that make them suitable for different applications and scenarios. Nevertheless, keeping the pace with constantly evolving scenarios and user's needs, for example in terms of offered quality or consumed power, is not that simple, and has led to continuous releases/updates of standards and profiles.Ideally designers should be allowed, at design-time, to select and combine coding tools and profiles to optimally match the given requirements, while guaranteeing that customized applications are still interoperable. Nevertheless, monolithic specifications tend to hide parallelism and the dataflow nature of video coding algorithms that, on the contrary, can be successfully exploited to guarantee efficient implementations and to play with different trade-offs [8].To address these issues, related to codecs design and customization, designers have been called to conceive efficient design-time methodologies

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Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers

Cited by 22 publications

References 31 publications

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Improving the Quality of Left-Behind Children’s Participation in Sports through Wireless Network Monitoring

Reconfigurable and approximate computing for video coding

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