Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration

Isa, Zaidi; Nabina, A.; Canagarajah, C N; Nunez-Yanez, Jose

doi:10.1109/dsd.2008.92

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…The The PR technology has been introduced in the microprocessor architecture design as well. For example in Zaidi et al (2008), the authors explore the utilization of run-time reconfiguration in the LEON3 open-source soft core processor. With reduced power consumption and area utilization accomplished, this work exposes the possibility of multiplexing different arithmetic functions tightly coupled to the integer pipeline and mapping them to the same silicon area.…”

Section: Applicationsmentioning

confidence: 99%

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications

Liu

Kuehn

et al. 2012

International Journal of Embedded and Real-Time Communication Systems

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FPGA Dynamic Partial Reconfiguration (DPR or PR) technology has emerged and become gradually mature in the recent years. It provides the Time-Division Multiplexing (TDM) capability in utilizing on-chip resources and leads to significant benefits in comparison with conventional static designs. However, the partially reconfigurable design process features additional complexity and technical requirements to the FPGA developers. Hence, PR design approaches are being widely explored and investigated to systematize the development methodology and ease the designers. In this paper, the authors collect several research and engineering projects in this area and present a survey of the design methodology and applications of PR. Research aspects are discussed in various hardware/software layers.

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Section: Applicationsmentioning

confidence: 99%

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications

Liu

Kuehn

et al. 2012

International Journal of Embedded and Real-Time Communication Systems

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Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

Fons

Cantó

et al. 2011

J Real-Time Image Proc

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This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.Peer ReviewedPostprint (published version

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