Power and performance evaluation of globally asynchronous locally synchronous processors

Abstract

Abstract

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

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“…In early work on this topic [20,21], they consider opportunities of DVFS application to GALS. They found that GALS designs are initially less efficient than synchronous architecture but that there are internal slacks that could be exploited.…”

“…For example, in some MCD designs, the floating point unit could be clocked much more slowly than the instruction fetch unit because its throughput and latency demands are lower. Iyer and Marculescu [20] show that for a GALS processor with five clock domains, the drop in performance ranges between 5% and 15%, while power consumption is reduced by 10% on the average. Thus, fine-grained voltage scaling allows GALS to match or exceed the power efficiency of fully synchronous approaches.…”

Accelerating Processors with Simple Touches

“…Hsu [5] proposed a compiler directed dynamic frequency and voltage scaling mechanism. Iyer [6] evaluated power and performance of globally asynchronous locally synchronous processors. Milutinovic [7] worked on pipeline design tradeoffs on the basis of a 32-bit gallium arsenide processor.…”

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

“…In the multiple clock domain (MCD) [35] technique, the hardware is separated into modules based on certain attributes, with each domain having its own clock. The synchronization of domains and power reduction in this technique are referred to as The globally-asynchronous locally-synchronous (GALS) design is one of the popular techniques to implement MCD systems, and the available power-reduction techniques are also beneficial for this kind of implementation [36]. The supply voltage of MCD may be uniform.…”