Power Amplifier Behavioral Modeling by Neural Networks and Their Implementation on FPGA

Abstract

In this paper, field programmable gate array (FPGA) implementation of two power amplifier (PA) dynamic behavioral modeling approaches with real-valued time-delay neural network (RVTDNN) and real-valued recurrent neural network (RVRNN) architectures are presented. The proposed PA models are based on the multilayer perceptron (MLP) neural networks with delayed inputs to take into account nonlinearity and memory effects of the PA. The synoptic weights of these neural networks are dynamically updated in order to prevent any eventual change in the PA's characteristics. Both architectures have been optimized to include only six hidden neurons and implemented on FPGA using Xilinx system generator. The FPGA is preferred to the digital signal processor (DSP) because it allows parallel computation tasks and software like flexibility. The modeling performances of these architectures are compared using 16-QAM modulated test signal. The mean square error (MSE) between the desired and the actual outputs of these models are also compared.

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

“…The most challenging part is that the NN could consume most of the available multipliers inside the FPGA. As an example, Ntoune et al [14] have implemented a real-valued time-delay neural network (RVTDNN) and real-valued recurrent neural network (RVRNN) architecture with 600 Wavelet Theory and Its Applications and 720 multipliers, respectively, while ML605 [15], ZC706 [16], and VC707 [17] have 768, 900, and 2800 multipliers (DSP48Es), respectively.…”