Power agnostic technique for efficient temperature estimation of multicore embedded systems

Rai, Devendra; Yang, Hoeseok; Bacivarov, Iuliana; Thiele, Lothar

doi:10.1145/2380403.2380421

Cited by 14 publications

(6 citation statements)

References 26 publications

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“…However, this technique considers a uni-processor system; therefore it fails to model the spatial temperature dependency when applied to multiprocessor systems. Finally, both the temporal (transient and steady-state) and the spatial dependency are modeled in [20], [21] using thermal characterization. However, the cyclic dependency between power and temperature is not considered.…”

Section: Related Workmentioning

confidence: 99%

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems

Das

Kumar

Veeravalli

2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Lifetime reliability is an emerging concern in multiprocessor systems as escalating power density and hence temperature variation continues to accelerate wear-out leading to a growing prominence of device defects. In this paper, we propose a system-level approach that involves performance-aware mapping of multimedia applications on a multiprocessor system to jointly minimize energy consumption and temperature related wear-out. Fundamental to this approach is a simplified temperature model that incorporates not only the transient and the steady-state behavior (temporal effect), but also the temperature dependency on the surrounding cores (spatial effect). This model is validated against the temperature obtained using the HotSpot tool with transient and steady-state simulations, and is shown to be accurate within 5.5 • C, leading to an MTTF estimation accuracy of an average 21% with respect to the state-of-the-art approaches. The proposed temperature model is integrated in a gradient-based fast heuristic that controls the voltage and frequency of the cores to limit the average and peak temperature leading to a longer lifetime, simultaneously minimizing the energy consumption. Lifetime computation considers task remapping, which is a common feature available in modern multiprocessor systems. A linear programming approach is then proposed to distribute the cores of a multiprocessor system among concurrent applications to maximize the lifetime. Experiments conducted with a set of synthetic and real-life applications represented as synchronous data flow graphs demonstrate that the proposed approach minimizes energy consumption by an average 24% with 47% increase in lifetime. For concurrent applications, the proposed lifetime-aware core distribution results in an average 10% improvement in lifetime as compared to performance-based core distribution.Index Terms-Lifetime reliability, mean time to failure (MTTF), platform-based design, synchronous data flow graphs.

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Section: Related Workmentioning

confidence: 99%

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems

Das

Kumar

Veeravalli

2016

IEEE Trans. Parallel Distrib. Syst.

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“…More specifically, it is highly likely that run-time compromise of an application results in a temperature trace that does not match its original thermal fingerprint. It has been shown to be possible to extract thermal models by monitoring the application under controlled conditions [48,49]. By comparing the actual execution trace to the expected trace, it may be possible to detect run-time compromise of software applications but this needs further exploration.…”

Section: Discussionmentioning

confidence: 99%

Thermal Covert Channels on Multi-core Platforms

Masti,

Rai,

Ranganathan

et al. 2015

Preprint

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Side channels remain a challenge to information flow control and security in modern computing platforms. Resource partitioning techniques that minimise the number of shared resources among processes are often used to address this challenge. In this work, we focus on multicore platforms and we demonstrate that even seemingly strong isolation techniques based on dedicated cores and memory can be circumvented through the use of thermal side channels. Specifically, we show that the processor core temperature can be used both as a side channel as well as a covert communication channel even when the system implements strong spatial and temporal partitioning. Our experiments on an x86-based platform demonstrate covert thermal channels that achieve up to 12.5 bps and a weak side channel that can detect processes executed on neighbouring cores. This work therefore shows a limitation in the isolation that can be achieved on existing multi-core systems.

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“…temperature trace from the corresponding sensor. Similar to previous work [19,24,29], we use the linear block with transfer function H(f ) to model the temperature variations at the sensor caused by the execution trace. The additive noise q(k) models thermal noise and any disturbances from other apps or the OS.…”

Section: Communication Channel Modelmentioning

confidence: 99%

On the capacity of thermal covert channels in multicores

Bartolini

Miedl

Thiele

2016

Proceedings of the Eleventh European Conference on Computer Systems

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Modern multicore processors feature easily accessible temperature sensors that provide useful information for dynamic thermal management. These sensors were recently shown to be a potential security threat, since otherwise isolated applications can exploit them to establish a thermal covert channel and leak restricted information. Previous research showed experiments that document the feasibility of (lowrate) communication over this channel, but did not further analyze its fundamental characteristics. For this reason, the important questions of quantifying the channel capacity and achievable rates remain unanswered. To address these questions, we devise and exploit a new methodology that leverages both theoretical results from information theory and experimental data to study these thermal covert channels on modern multicores. We use spectral techniques to analyze data from two representative platforms and estimate the capacity of the channels from a source application to temperature sensors on the same or different cores. We estimate the capacity to be in the order of 300 bits per second (bps) for the same-core channel, i.e., when reading the temperature on the same core where the source application runs, and in the order of 50 bps for the 1-hop channel, i.e., when reading the temperature of the core physically next to the one where the source application runs. Moreover, we show a communication scheme that achieves rates of more than 45 bps on the same-core channel and more than 5 bps on the 1-hop channel, with less than 1% error probability. The highest rate shown in previous work was 1.33 bps on the 1hop channel with 11% error probability.

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Power agnostic technique for efficient temperature estimation of multicore embedded systems

Cited by 14 publications

References 26 publications

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems

Thermal Covert Channels on Multi-core Platforms

On the capacity of thermal covert channels in multicores

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