Potential Induced Degradation of solar cells and panels

Abstract

Since solar energy generation is getting more and more important worldwide PV systems and solar parks are becoming larger consisting of an increasing number of solar panels being serially interconnected. As a consequence panels are frequently exposed to high relative potentials towards ground causing High Voltage Stress (HVS). The effect of HVS on long term stability of solar panels depending on the leakage current between solar cells and ground has been first addressed by NREL in 2005 [1). This potential degradation mechanism is not monitored by the typical PV tests listed in lEG 61215 [2). Depending on the technology different types of Potential Induced Degradation (PIO) occur. This paper is focusing on PIO of wafer based standard p-type silicon technology aiming on increasing life times for solar panels once exposed to external potentials in the field. A test setup is presented for simulation of the PIO in the lab and the influence of cell properties on PIO is demonstrated in order to reveal the cell being the precondition for the PIO. However, PIO can also be stopped or minimized on panel and system level as shown in the paper. BACKGROUND

Interlaboratory Study to Determine Repeatability of the Damp-Heat Test Method for Potential-Induced Degradation and Polarization in Crystalline Silicon Photovoltaic Modules

“…In the last decade, polarization [3] and potential-induced degradation (PID) [4] have come to be understood as critically important failure mechanisms that are not examined in standardized testing. Mechanistic aspects of PID occurring in conventional crystalline silicon films have been studied by Neumann and coworkers [5].…”

Potential‐induced optimization of ultra‐thin rear surface passivated CIGS solar cells

“…Note that the unpassivated reference cells have the same processing sequence, but without the formation of the advanced rear passivation structure (steps 3-5 in Table 1). An electrical field strength of +50 or -50 V DC /mm glass thickness is applied between the backside of the SLG and the SLG/Mo interface, two approaches previously called "potential induced degradation" (PID) or "accelerated recovery", respectively [11][12][13]. To be able to induce such electrical fields to those cells, first a few extra steps are needed: (i) the sample backside and edges are etched with dilute HCl to remove any conductive paths between the contacts for the external voltage created by the deposition of CdS and/or ZnO:Al, (ii) an electrical contact is applied to the backside of the substrate by means of aluminium tape, and (iii) an electrical contact is soldered to the Mo back contact of the solar cell stack, see [13] for a picture and sketch.…”

“…The samples are exposed to a temperature of 85 °C in air atmosphere with an applied bias of ±50 V between the glass substrate and the Mo (ground). In case of +50 V, this approach is called PID, as designated and explained in [11][12][13]. In case of -50 V, the approach is called accelerated recovery, as designated and explained in [13].…”

“…It is known that a typical way to migrate Na in CIGS solar cells is to use an electric field between the backside of the SLG and the SLG/rear-contact interface [11][12][13]. Therefore, the impact of such electrical fields on the cell performance of Al 2 O 3 rear surface passivated CIGS solar cells is investigated and correlated to elemental Na depth profiles in the absorber layer.…”

Research on the Power Drop of Photovoltaic Module’s Aging Through the Thermal Shock Test

“…In solar cells, micro-crack is a genuine defect of photovoltaic (PV) modules [1][2][3]. It is difficult to prevent these cracks from developing in solar cells.…”