Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor

Abstract

simulated clock power at various operation modes (cold/warm reset, power-down, memory read/write, low frequency test As performance per Watt concept being adapted on CPU's modes). In order to evaluate the issues of higher chip power performance, a comprehensive post-silicon design consumption, product yield loss from high leaky units, and methodology on chip power characterization, debug, and product reliability, it becomes a necessary to establish a validation developed for an energy-efficient product systematic, reusable, as well as technology scalable postperformance become ever more important. An infrared silicon design methodology to manage power performance photon-emission (IREM) based technique has been problems. established to meet the needs. With those developed tool This paper describes an Infrared Emission Microscopy capabilities, we can validate simulated fullchip power, (IREM) based comprehensive methodology and tools built determine the causes of excessive power leakage, generate die around it by taking advantage of backside image and photons power and thermal maps, and eventually optimize follow-on emission features [3]. Engineers are capable of conducting designs for power performance. This newly developed validation on power-saving designs, generating fullchip power techniques have been applied and proven reusable on multiple and temperature maps, and conducting a root cause analysis core microprocessors fabricated under 90nm and 65nm CMOS on excessive static and dynamic power leakage, and technology. Examples of 5-8% power saving as compared calculating the package thermal resistance for thermal with the first silicon data are presented here to demonstrate the managements at platform. The key impacts to final product success on debug and design optimization on fullchip power.performance include a design optimization on power network delivery and usage models, elimination of possible reliability I. Introductions issues introduced leaky transistors, relaxation reliability design rules on selected follow-on designs, and enhancement As Moore's law continues on high performance multipleof layout rules for process variations etc.. core microprocessors fabricated on nanometer CMOS technology, the scopes of design challenge on total chip power II. Pre-Silicon Power Modeling and Power Equations consumption, peak power density, power leakage, and heat generation becomes wider and more complicated. Wide range A simplified fullchip power can be modeled as: of advanced power-saving and thermal management P total = Pstatic + Pdyn + Prt + Pbug (1) techniques have been implemented on those microprocessors where, with features of higher core clock frequency, larger chip P total: Fullchip power at given test corners and excised patterns power, denser layout, and smaller feature size of devices.Pstatic: Leakage current generated from gate leakage(Pgate), subMany known power-saving techniques can be found on published company's article [1] such as: architecture threshold source/drain channel leakage(Pchannel), and ...