Post deposition annealing effect on the properties of Al2O3/InP interface

Kim, Hogyoung; Kim, Dong Ha; Choi, Byung Joon

doi:10.1063/1.5019856

Cited by 1 publication

(2 citation statements)

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“…Experimental study regarding interface property of

{italicAl}_{2} O_{3} / InP

interface suggest that the range of trap density (

D_{italicit}

) lies in between

5 \times 10^{11} - 5 \times 10^{12} {cm}^{‐ 2} {eV}^{‐ 1}

. 22,25,26 We have used

D_{italicit} = 1 \times 10^{12} {cm}^{‐ 2} {eV}^{‐ 1}

for

{italicAl}_{2} O_{3} / InP

interface. Simularly, a

D_{italicit}

value of

1 \times 10^{13} {cm}^{‐ 2} {eV}^{‐ 1}

is considered for

HZO / {Al}_{2} {normalO}_{3}

interface 27 .…”

Section: Device Description and Numerical Simulation Frameworkmentioning

confidence: 99%

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Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

Maity

Basak

Das

2022

Int J Numerical Modelling

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Negative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different DC and analog figure of merits such as on current (ION), switching ratio (ION/IOFF), threshold voltage roll‐off, sub‐threshold swing (SS), trans‐conductance (gm), transconductance efficiency (gm/ID) of the test device has been analyzed for different ferroelectric layer thicknesses and compared with the baseline device. We have investigated RF performance such as gate capacitance, unity‐gain cut‐off frequency and small signal voltage gain of the device. Improvement in DC and analog figure of merits is proportional to the ferroelectric layer thickness. However, for higher values of ferroelectric thickness, the hysteresis effect gradually became prominent. MOS transistor with optimum ferroelectric layer thickness shows the negligible amount of threshold voltage roll‐off and improved transconductance‐frequency product compared to the baseline device. In presence of ferroelectric layer, the effect of channel thickness variation on device performance is reduced. The role of ferroelectric gate stack is found to be more prominent at shorter gate length.

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“…Experimental study regarding interface property of

{italicAl}_{2} O_{3} / InP

interface suggest that the range of trap density (

D_{italicit}

) lies in between

5 \times 10^{11} - 5 \times 10^{12} {cm}^{‐ 2} {eV}^{‐ 1}

. 22,25,26 We have used

D_{italicit} = 1 \times 10^{12} {cm}^{‐ 2} {eV}^{‐ 1}

for

{italicAl}_{2} O_{3} / InP

interface. Simularly, a

D_{italicit}

value of

1 \times 10^{13} {cm}^{‐ 2} {eV}^{‐ 1}

is considered for

HZO / {Al}_{2} {normalO}_{3}

interface 27 .…”

Section: Device Description and Numerical Simulation Frameworkmentioning

confidence: 99%

“…. 22,25,26 We have used D it ¼ 1 Â 10 12 cm -2 eV -1 for Al 2 O 3 =InP interface. Simularly, a D it value of 1 Â 10 13 cm -2 eV -1 is considered for HZO=Al 2 O 3 interface.…”

Section: Setting Up Numerical Simulation Frameworkmentioning

confidence: 99%